An Efficient Interconnect Test Pattern Generation Algorithm for Crosstalk Faults
![]() |
Han, Ju-Hee
(Department of Computer Science & Engineering, Hanyang University)
Song, Jae-Hoon (Department of Computer Science & Engineering, Hanyang University) Yi, Hyun-Bean (Department of Computer Science & Engineering, Hanyang University) Kim, Jin-Kyu (Department of Computer Science & Engineering, Hanyang University) Park, Sung-Ju (Department of Computer Science & Engineering, Hanyang University) |
1 | N. Jarwala and C. W. Yau, 'A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects,' in Proc. IEEE Int. Test Conf., 1989, pp. 63 - 70 |
2 | X. Bai, S. Dey and J. Rajski, 'Self-test methodology for at-speed test of crosstalk in chip interconnects,' in Proc. ACM/IEEE Design Automation Conf., 2000, pp. 619 - 624 |
3 | K. Sekar and S. Dey, 'LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects,' in Proc. VLSI Test Symp., 2002, pp. 417 - 422 |
4 | P. Min et. al, 'Efficient Interconnect Test Patterns for Crosstalk and Static Faults', IEEE Trans. on Computer-Aided Design, vol. 25, No. 11, pp. 2605 - 2608, Nov. 2006 DOI ScienceOn |
5 | W. T. Cheng, J. L. Lewandowski, and E. Wu, 'Optimal diagnostic methods for wiring interconnects,' IEEE Trans. on Computer-Aided Design, vol. 11, No. 9, pp. 1161-1166, Sept. 1992 DOI ScienceOn |
6 | Sungju Park, 'A new complete diagnosis patterns for wiring interconnects,' in Proc. IEEE Design Automation Conf. 1996, pp. 203 - 208 |
7 | M. Cuviello, S. Dey, X. Bai, and Y. Zhao, 'Fault modeling and simulation for crosstalk in system-on-chip interconnects,' in Proc. Int. Computer-Aided Design Conf., 1999, pp. 297-303 |
8 | H. Zhou and D. F. Wang, 'Global Routing with Crosstalk Constaints', in Proc. IEEE Design Automation Conf., 1988, pp. 374-377 |
9 | A. Hassan, J. Rajski, and V.K. Agrawal, 'Testing and diagnosis of interconnects using boundary scan architecture,' in Proc. IEEE Int. Test Conf., 1988, pp.126-137 |
10 | R. Pendurkar, A. Chatterjee, and Y. Zorian, 'Switching activity generation with automated BIST synthesis for performance testing of interconnects,' IEEE Trans. on Computer-Aided Design, vol. 11, No. 9, pp. 1143 - 1158, Sept. 2001 |
11 | W. Sirisaengtaksin and S. K. Gupta 'Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology,' in Proc. IEEE Asian Test Symp., 2002, pp. 163 - 169 |
![]() |