• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.241-241
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• 2009

For the Radio Frequency Integrated Passive Device (RFIPD) application, we have successfully developed and characterized high break-down voltage metal-insulator-metal (MIM) capacitors with 2,000 ${\AA}$ plasma-enhanced chemical vapor deposition (PECVD) silicon nitride which deposited with $SiH_4/NH_3$ gas mixing rate, working pressure, and RF power of PECVD at $250^{\circ}C$ chamber temperature. At the PECVD process condition of gas mixing rate (0.957), working pressure (0.9 Torr), and RF power (60 W), the AFM RMS value of about 2,000 ${\AA}$ silicon nitride on the bottom metal was the lowest of 0.862 nm and break-down electric field was the highest of about 8.0 MV/cm with the capacitance density of 326.5 $pF/mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.46-47
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• 2009

In this paper, a power combiner using IPD process for SK Telecom 3-Generation (2.13 ~ 2.15 GHz) application. The Integrated Passive Device (IPD) Wilkinson power Combiner shows compact size and high performance. It is simulated by 3D Electro Magnetic (EM) simulation because of more accurate measurement result wire-bonding effects. This combiner exhibit size of $1.2mm^2$ the insertion loss of 3.6 dB, and the return loss of 10.1 dB, and isolation of more than -7.7 dB.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.359-359
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• 2006

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.385-386
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• 2008

In this paper, a simple dual band filter chip is designed with 0603 case size using IPD technology. The dual-band filter achieves high frequency band at 2.5 GHz and low frequency band at 1.8 GHz. The insertion losses in high frequency band and low frequency band are -0.195 dB and -0.146 dB, respectively. The return losses in these bands are -22.7 dB and -22.8 dB, respectively. The simple dual-band filter based on SI-GaAs substrate is designed within die size of about 1.3 $mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.184-184
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• 2008

In this paper, a power divider with a multi-band and broadband are designed and fabricated using an InGaP/GaAs process. The design of this divider is based on multi-band because it is important in the next generation IMT-Advances system. In this design, power divider is fabricated with the frequency of 824 MHz to 894 MHz, 1.8 GHz to 2.2 GHz and 2.3 GHz to 2.4 GH for cellular, personal communication system (PCS) and Wireless Broadband Internet (WiBro). The topology of the designed power divider is based on the multi-section and fabricated using integrated passive device (IPD) library of nanoENS Inc. It is measured using network analyzer.

• Current Optics and Photonics
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• v.5 no.6
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• pp.711-720
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• 2021

A novel optical hybrid device that doubles the multilevel demodulation resolution by adding the optical interferometer with a waveguide crossover is proposed, theoretically analyzed and experimentally verified. We report two types of all-passive phase control schemes that will be referred to as a phase compensation scheme and a phase optimization scheme. We also apply the proposed phase control schemes to a 45° optical hybrid consisting of two parallel 90° optical hybrids together with the proposed phase control scheme for demodulating 8-level differential phase shift keying optical signals. Octagonal phase response with low wavelength sensitive excess loss of <0.8 dB over 31-nm-wide spectral range will be demonstrated in the InP-based material platform.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.167-170
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• 2021

Integrated passive device (IPD) technology has emerged with the need for 5G. In order to integrate and miniaturize capacitors inside IPD, various studies are actively performed using high-k materials and trench structures. In this paper, an EM(Electromagnetic) simulation study was performed by applying an oxide dielectric to the capacitors having a various trench type structures. Commercially available materials HfO₂, Al₂O₃, and Ta₂O₅ are applied to non, circle, trefoil, and quatrefoil type trench structures to confirm changes in each material or structure. As a result, the bigger the capacitor area and the higher dielectric constant of the oxide dielectric, the insertion loss tended to decrease.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• Transactions on Electrical and Electronic Materials
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• v.10 no.5
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• pp.147-151
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• 2009

For integrated passive device (IPD) applications, we have successfully developed and characterized metalinsulator-metal (MIM) capacitors with 2000 $\AA$ plasma-enhanced chemical vapor deposition (PECVD) silicon nitride which are deposited with the $SiH_4/NH_3$ gas mixing rate, working pressure, and RF power of PECVD at $250^{\circ}C$. Five PECVD process parameters are designed to lower the refractive index and lower the deposition rate of $Si_3N_4$ films for the high breakdown electric field. For the PECVD process condition of gas mixing rate (0.957), working pressure (0.9 Torr), and RF power (60 W), the atomic force microscopy (AFM) root mean square (RMS) value of about 2000 $\AA$ $Si_3N_4$ on the bottom metal is lowest at 0.862 nm and the breakdown electric field is highest at about 8.0 MV/cm with a capacitance density of 326.5 pF/$mm^2$. A pretreatment of metal electrodes is proposed, which can reduce the peeling of nitride in the harsh test environment of heat, pressure, and humidity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.