• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.92-92
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• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.355-355
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• 2010

We studied the dependence of the performance of schottky barrier metal-oxide-field effect transistors(SB MOSFETs) on the work function of source/drain metals. A strong impact of the various work functions and the light wavelengths on the transistor characteristics is found and explained using experimental data. We used an insulator of a high thickness (100nm) and back gate issues in SOI substrate, subthreshold swing was measured to 300~400[mV/dec] comparing with a ideal subthreshold swing of 60[mV/dec]. Excellent characteristics of Al/Si was demonstrated higher on/off current ratios of ${\sim}10^7$ than others. In addition, extensive photoresponse analysis has been performed using halogen and deuterium light sources(200<$\lambda$<2000nm).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.58-68
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• 1995

Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.

• 전기의세계
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• v.18 no.1
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• pp.11-14
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• 1969

This paper shows experimentally one method of preventing porcelain insulators from salt accident likely to be caused in the region of sea coast. In this experiment some results that, if a conductor barrier is inserted into the flash over discharge path which is wetted by salt dissolved water, the flash over voltage found to be raised up, were gotten. This results may be actually applied to suspension insulator or bushing to prevent them from salt accidents.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.800-803
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• 2002

The MONOS capacitor are fabricated to investigate the carrier trapping due to Fowler-Nordheim tunneling injection. The carrier trapping in scaled multi-dielectric(ONO) depends on the nitride and Op oxide thickness under Fowler_Nordheim tunneling injection. Carriers captured at nitride film could not escape from nitride to gate, but be captured at top oxide and nitride interface traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices using multi dielectric films enhance memory effect and have a long memory retention characteristic.

• Journal of the Korean Magnetics Society
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• v.15 no.6
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• pp.311-314
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• 2005

We investigated the composition dependence of the tunneling magnetoresistance (TMR) behavior and the stability of the magnetic tunnel junctions (MTJs) with TiAlOx barrier and the microstructural evolution of TiAl alloy films. The TMR ratio increased up to $49\%$ at $5.33\;at\%$ Ti. In addition, a significant tunneling magnetoresistance (TMR) value of $20\%$ was maintained after annealing at $450^{\circ}C$, and the breakdown voltage ($V_B$) of and 1.35 V were obtained in the MTJ with $5.33\;at\%$ Ti-alloyed AlOx barrier. These results were closely related to the enhanced quality of the barrier material microstructure in the pre-oxidation state. Ti alloying enhanced the barrier/electrode interface uniformity and reduced microstructural defects. These structural improvements enhanced not only the TMR effect but also the thermal and electrical stability of the MTJs.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1125-1128
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• 2002

Tantalum pentoxide (Ta$_2$O$\sub$5/) is a candidate for use in metal-insulator-metal diode in switching devices for active-matrix liquid-crystal displays. The MIM diode with very low threshold voltage and perfect symmetry was fabricated. High quality Ta$_2$O$\sub$5/ thin films were obtained by using an anodizing method. Rutherford backscattering spectroscopy, transmission electron microscope observations, auger electron spectroscopy, ellipsometry measurements, and electrical measurements, such as current - voltage(I-V) measurements were performed to investigate Ta$_2$O$\sub$5/ films and their reliability and indicated that the obtained TaOx thin films were reliable Ta$_2$O$\sub$5/ films for the applications. Furthermore, in this paper, we discuss the effects of top-electrode metals and annealing conditions. The conduction mechanism of the leakage current and the symmetry characteristics related to the Schottky emission and Poole-Frankel effect are also discussed using the results of electrical measurements and conduction barrier theory.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• Korean Journal of Materials Research
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• v.28 no.5
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• pp.268-272
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• 2018

An $Al_2O_3/AlN$ bilayer deposited on GaN by atomic layer deposition (ALD) is employed to prepare $Al_2O_3/AlN/GaN$ metal-insulator-semiconductor (MIS) diodes, and their interfacial properties are investigated using X-ray photoelectron spectroscopy (XPS) with sputter etch treatment and current-voltage (I-V) measurements. XPS analyses reveal that the native oxides on the GaN surface are reduced significantly during the early ALD stage, indicating that AlN deposition effectively clelans up the GaN surface. In addition, the suppression of Al-OH bonds is observed through the ALD process. This result may be related to the improved device performance because Al-OH bonds act as interface defects. Finally, temperature dependent I-V analyses show that the barrier height increases and the ideality factor decreases with an increase in temperature, which is associated with the barrier inhomogeneity. A Modified Richardson plot produces the Richardson constant of $A^{**}$ as $30.45Acm^{-2}K^{-2}$, which is similar to the theoretical value of $26.4Acm^{-2}K^{-2}$ for n-GaN. This indicates that the barrier inhomogeneity appropriately explains the forward current transport across the $Au/Al_2O_3/AlN/GaN$ interface.