• Title/Summary/Keyword: input delay system

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Effect of Dimension Reduction on Prediction Performance of Multivariate Nonlinear Time Series

  • Jeong, Jun-Yong;Kim, Jun-Seong;Jun, Chi-Hyuck
    • Industrial Engineering and Management Systems
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    • v.14 no.3
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    • pp.312-317
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    • 2015
  • The dynamic system approach in time series has been used in many real problems. Based on Taken's embedding theorem, we can build the predictive function where input is the time delay coordinates vector which consists of the lagged values of the observed series and output is the future values of the observed series. Although the time delay coordinates vector from multivariate time series brings more information than the one from univariate time series, it can exhibit statistical redundancy which disturbs the performance of the prediction function. We apply dimension reduction techniques to solve this problem and analyze the effect of this approach for prediction. Our experiment uses delayed Lorenz series; least squares support vector regression approximates the predictive function. The result shows that linearly preserving projection improves the prediction performance.

THE ROOT CAUSE ANALYSIS PROCESS FOR SCHEDULE DELAY IN CONSTRUCTION (건설공사의 작업지연 원인분석 프로세스)

  • Ji, Kun-Chang;Kim, Chang-Duk;Yu, Jung-Ho
    • Korean Journal of Construction Engineering and Management
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    • v.7 no.5
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    • pp.138-148
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    • 2006
  • In constructing projects, there exist various kinds of work interferences, which cause a delay of the outset and completion of planned schedule because of some attributions, such as variability, uncertainty and complexity, and so schedule delay has been treated as a natural phenomenon. To reduce or prevent the schedule delay, a constant confirmation of schedule delay and a preparation of counter plans for finding out the cause structure of schedule delay should have been done. However, all this time the research has been mostly done on the calculation method or claim cases of schedule delay, and the range of analysis method of the cause structure of schedule delay has been multifarious from industrial views to views of specific work. Moreover, the classifying system and analysis method did not consider the trait, which cause the schedule delay, in constructing projects. For this reason, it is difficult to compare the cause of delay factors of the projects and to understand the effect of schedule delay by each factor. This paper restricts the range of the cause analysis of schedule delay to the field of site management in the projects and divides the cause structure of schedule delay into the cause objects and cause attributes of schedule delay according to the input elements. The system of classifying causes of schedule delay is examined by interviews with experts and questionnaire. Additionally, this paper analyzes the attributes of cause attributes and cause subjects and presents the analysis method and procedure of schedule delay with the application of VSM.

Robust Backstepping Control Using Time Delay Estimation (시간 지연 추정을 이용한 강인 Backstepping 제어)

  • Kim, Seong-Tae;Chang, Pyung-Hun;Kang, Sang-Hoon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.28 no.12
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    • pp.1833-1844
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    • 2004
  • A controller is proposed for the robust backstepping control of a class of nonlinear multiple-input multiple-output (MIMO) systems which can be converted to a strict feedback form. The proposed robust backstepping control scheme follows a systematic procedure for the design of control laws and uses time delay estimation (TDE) to estimate the uncertainties such as parameter variations, unknown disturbances, and unmodeled dynamics, etc. The proposed controller can be also applied to nonlinear MIMO systems with unmatched uncertainties. Stability analysis of the closed-loop system which contains the plant and the proposed controller is also studied and hereby a sufficient stability condition for the closed-loop system is proposed. The simulation results show that the control scheme works well with uncertainties and the proposed stability condition is valid. The controller is experimentally verified on a single-link flexible arm to show the effectiveness of the proposed scheme in the complicated systems with uncertainties.

Analysis of the LED Lamp Arrangement for Uniformity of Illumination in Indoor VLC System

  • Hao, Hong-Gang;Zhang, Dan-Dan;Tang, Shuai
    • Journal of the Optical Society of Korea
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    • v.18 no.6
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    • pp.663-671
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    • 2014
  • LED lamp arrangement is a critical issue in indoor visible light communication (VLC) system. In this paper, we analyze the illumination distribution under the arrangement of $2{\times}3$ and propose a method to find the optimal lamp arrangement. The method, based on the MIMO (Multiple Input/Multiple Output) system model and taking the first order reflection into consideration, enables accurate analysis of the arrangement of the LED lamps for any room. The studies show that under the optimal arrangement the uniformity of illumination is improved from 0.55 to 0.86, which guarantees that users can get almost equal lighting effects, no matter where they locate themselves. At the same time, the RMS delay spread distribution which is used to evaluate the inter-signal-interference (ISI) is analyzed, and the simulation results indicate that the optimal arrangement also can improve the communication quality by reducing the fluctuation of the RMS delay spread.

Time delay estimation by iterative Wiener filter based recursive total least squares algorithm (반복형 위너 필터 방법에 기반한 재귀적 완전 최소 제곱 방법을 사용한 시간 지연 추정 알고리즘)

  • Lim, Jun-Seok
    • The Journal of the Acoustical Society of Korea
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    • v.40 no.5
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    • pp.452-459
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    • 2021
  • Estimating the mutual time delay between two acoustic sensors is used in various fields such as tracking and estimating the location of a target in room acoustics and sonar. In the time delay estimation methods, there are a non-parametric method, such as Generalized Cross Correlation (GCC), and a parametric method based on system identification. In this paper, we propose a time delay estimation method based on the parametric method. In particular, we propose a method that considers the noise in each receiving acoustic sensor. Simulation confirms that the proposed algorithm is superior to the existing generalized cross-correlation and adaptive eigenvalue analysis methods in white noise and reverberation environments.

A Study on the Universal Motor Speed Controller for Eliminating Harmonic Current (고조파전류 감쇠용 유니서셜모터 속도제어기에 관한 연구)

  • Lim, Hong-Woo;Cho, Geum-Bae;Baek, Hyung-Lae;Jang, Young-Hae;Sin, Sa-Hyeon
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.1151-1154
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    • 2000
  • Phase angle control ac drives system gains a high popularity due to their simple implementation despite the disadvantage of their poor input power factor especially for large values of phase delay angle. Furthermore it generates subharmononic current at specific phase angle. As input current of do drive systems are sinusoidal, the power factor and subharmonic current characteristics are improve. This paper presents the application of a PWM control technique of do chopper system to reduce the subharmonic current and its characteristics using single-phase dc chopper drive system of universal motor.

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Performance study of the priority scheme in an ATM switch with input and output queues (입출력 큐를 갖는 ATM 스위치에서의 우선순위에 관한 성능 분석)

  • 이장원;최진식
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.2
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    • pp.1-9
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    • 1998
  • ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

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A Study of 0.5-bit Resolution for True-Time Delay of Phased-Array Antenna System

  • Cha, Junwoo;Park, Youngcheol
    • International journal of advanced smart convergence
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    • v.11 no.4
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    • pp.96-103
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    • 2022
  • This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm2. In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

An Improvement of Implementation Method for Multi-Layer AHB BusMatrix (ML-AHB 버스 매트릭스 구현 방법의 개선)

  • Hwang Soo-Yun;Jhang Kyoung-Sun
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.11_12
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    • pp.629-638
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    • 2005
  • In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

A Study on The Optimal Data Link Window Flow Control for ISDN (ISDN을 위한 최적 데이타 링크 흐름 제어에 관한 연구)

  • Kim, Dong-Yon;Shin, Woo-Cheol;Park, Mig-Non;Lee, Sang-Bae
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1174-1177
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    • 1987
  • The design of flow control protocols for integrared networks with complete voice traffic on the data link level is investigated. The class of admissible flow control policies analyzed maximized the average data link throughput subject to an average system time delay constraints a finite intervals (O,s). In particular, it is shown that the optimum control law is bang-bang (window flow mechanism). The window size L can be analytically derived from maximum tolerated time delay T, the input arrival C of the queueing system, the duration of the time interval S, the initial number of packets in the queue.

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