• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.309-314
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• 2014

This work proposes an integrated high frequency divider with an inductive peaking technique implemented in a current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop, and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupled n-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias is used for its high current driving capability and stable frequency response. The proposed divider is designed with $0.18-{\mu}m$ CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL) circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In the output frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an input frequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.22-29
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• 2007

A 2.5Gb/s 2:1 multiplexer(MUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. On-chip micro spiral inductor was designed to maximize the inductive peaking effect without increasing the chip area much. The designed 4.7 nH micro-spiral inductor was $20\times20{\mu}m2$ in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 23% and 3% respectively using the micro spiral inductors for 1.25Gb/s signal. For 2.5 Gb/s signal, fall and rise time was improved 5.3% and 3.5% respectively. It consumed 61mW and voltage output swing was 1$180mV_{p-p}$ at 2.5Gb/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.198-204
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• 2009

Inductive peaking using T-coils has been widely used in broadband I/O interfaces. In this paper, we analyze technical effects and limitations of the T-coil, and discuss several methods that can overcome these restrictions and improve the practicality of the T-coil. In particular we also propose and verify a circuit topology which can further extend bandwidth beyond the limit that conventional T-coil can achieve, and transfer 20 Gb/s data without noticeable distortion.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.11
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• pp.2127-2130
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• 2008

In this paper, a tunable bandpass filter with mutual inductive coupling circuits is newly designed and demonstrated for UHF TV tuner ranged from Ch.14(473MHz) to Ch.69(803MHz) applications. Conventional HF tuning circuit with an electromagnetic bandpass filter has several problems such as large size, high volume and high cost, since the electromagnetic filter is comprised of several passive components and air core inductors to be assembled and controlled manually. To address these obstacles, peaking chip inductor was newly applied for constructing the mutual inductive coupling circuit. The proposed circuit was newly and optimally designed, since the chip inductor showed lower components Q-value than the air core inductor. A varactor diode has been also used to fabricate the proposed tunable bandpass filter for RF tuning circuit. The fabricated tunable filter exhibited low insertion loss of approximately -3dB, high return loss of below -10dB, and large tuning bandwidth of 330MHz.

• Smart Media Journal
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• v.4 no.2
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• pp.55-61
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• 2015

A bandwidth-enhanced ultra-wide band (UWB) CMOS balun-LNA is implemented as a part of a software defined radio (SDR) receiver which supports multi-band and multi-standard. The proposed balun-LNA is composed of a single-to-differential converter, a differential-to-single voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband balun-LNA exploiting negative feedback is implemented. By adopting a source follower-based inductive shunt peaking, the proposed balun-LNA achieves a wider gain bandwidth. Two LNA design examples are presented to demonstrate the usefulness of the proposed approach. The LNA I adopts the CS amplifier with a common gate common source (CGCS) balun load as the S-to-D converter for high gain and low noise figure (NF) and the LNA II uses the differential amplifier with the ac-grounded second input terminal as the S-to-D converter for high second-order input-referred intercept point (IIP2). The 3 dB gain bandwidth of the proposed balun-LNA (LNA I) is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average power gain of 18 dB and an IIP3 of -8 ~ -2 dBm are obtained. In simulation, IIP2 of the LNA II is at least 5 dB higher than that of the LNA I with same power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1055-1063
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• 2013

Low noise amplifiers(LNAs) are an integral component of RF receivers and are frequently required to operate at wide frequency bands for various wireless systems. For wideband operation, important performance metrics such as voltage gain, return loss, noise figures and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high input matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor between gate and drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this LNA is $0.202mm^2$, including pads. Measurement results illustrate that input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 7~8 dB over 1.5~13 GHz. In addition, good linearity(IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• Journal of the Optical Society of Korea
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• v.12 no.4
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• pp.217-220
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• 2008

An optical receiver using a CMOS-compatible avalanche photodetector (CMOS-APD) is demonstrated. The CMOS-APD is fabricated with $0.18{\mu}m$ standard CMOS technology and the optical receiver is implemented by using the CMOS-APD and a transimpedance amplifier on a board. The optical receiver can detect 6.25-Gb/s data with the help of the series inductive peaking effect.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.900-905
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• 2009

A common drain feedback CMOS wideband LNA with current bleeding and input inductive series-peaking techniques is presented in this paper. DC coupling is adopted between cascode and feedback amplifiers, so that the gain and NF of the LNA can be dynamically controlled by adjusting the bleeding current. The fabricated LNA shows the bandwidth of 2.5 GHz. The high gain mode shows 17.5 dB gain with $1.7{\sim}2.8\;dB$ NF and consumes 27 mW power and the low gain mode has 14 dB gain with $2.7{\sim}4.0\;dB$ NF and dissipates 1.8 mW from 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.8
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• pp.717-724
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• 2016

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and low-power consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.