• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.455-457
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• 2003

In the present IEC 60427(2000), reduced applied voltage can be used for synthetic short-circuit making current tests if the maximum pre-arcing time of the test circuit breaker is less than $1/{\omega}$. But in the near future IEC, only the making tests with full test voltage shall be allowed. To meet this trend, KERI is preparing synthetic making test facilities using step-up transformer, ITMC and plasma making switch. This paper presents analytical characteristics of KERI's synthetic short-circuit making test circuits. The results of this paper can be useful for effective and adequate tests.

• Journal of Electrical Engineering and Technology
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• v.7 no.5
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• pp.778-783
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• 2012

The synthetic short-circuit making test to adequately stress the circuit breaker has been specified as the mandatory test duty in the IEC 62271-100. The purpose of this test is to give the maximum pre-arcing energy during making operation. And this requires the making operation with symmetrical short-circuit current that is established when the breakdown between contact gap occurs near the crest of the applied voltage. Also, if the interrupting chamber of circuit breakers is designed as the type of common enclosure or the operation is made by the gang operated mechanism that three-phase contacts are operated by one common mechanism, three-phase synthetic making test is basically required. Therefore, several testing laboratories have developed and proposed their own test circuits to properly evaluate the breaker performance. With these technical backgrounds, we have developed the new alternative three-phase making circuit.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.6
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• pp.287-292
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• 2001

This paper deals with the configuration, operating principles, systematic calculation method of parameter and optimization method of test circuit for parallel current injection method, series voltage injection method and hybrid synthetic test method as the method for performance test of circuit breaker with extra high interrupting capacity. The test method depicted above is applied to short-circuit making and breaking test (operating sequence :Os CdOs, Od-CdOs) and out-of-phase tests(operating sequence :Os, CdOs) for performance test of the newly-developed 420kV, 50kA and 800kV 50kV puffer-type gas circuit-breaker according to IEC 60056 and IEC 60427. The testing results, evaluation of equivalence for test and analyzed results are also presented in this paper.

• Journal of the Korean Society of Safety
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• v.37 no.6
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• pp.1-8
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• 2022

This study analyzed the characteristics of insulation resistance and operating time based on an accelerated degradation test of a low-voltage circuit breaker. The experimental sample used a molded case circuit breaker (MCCB) and an earth leakage circuit breaker (ELCB). After measuring the insulation resistance of the circuit breakers, the leakage current was affected by an external rather than an internal structure. Furthermore, the insulation resistance of the circuit breakers with accelerated degradation was measured using a Megger insulation tester. In the accelerated degradation test, aging times of five, ten, 15, and 20 years were applied according to a temperature derived using the Arrhenius equation. Circuit breakers with an equivalent life of ten, 15, and 20 years had increased insulation resistance compared to those with less degradation time. In particular, the circuit breaker with an equivalent life of ten years had the highest insulation resistance. Component analysis of the circuit breaker manufactured through an accelerated degradation test confirmed that the timing of the increase in insulation resistance and the time of additive loss were the same. Finally, after analyzing the operating time of the circuit breakers with degradation, it was confirmed that the MCCB did not change, but the ELCB breaker failed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1149-1152
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• 2003

Now a days, many different kinds of display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), and Liquid Crystal On Silicon (LCOS) are designed. And these display technologies will be used in many application products like High Definition Televisions (HDTVs) or mobile devices. In this paper, pattern generation circuit for display test is proposed. The proposed circuit will be embedded in the control circuit of display chip. Two differenct kinds of patterns is generated by the circuit. One is block pattern for color test, and the other is line pattern for pixel test. The shape of test pattern is determined by the values of registers in pattern generation circuit. The circuit is designed using Verilog HDL RTL code.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.8-15
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• 1993

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.9
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.896-904
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• 1987

In this paper, a design method for sequential circuit which is easy to have Built-in Self Test is kproposed using the functional advantages of multifunctional BILBO and LSSD. To achieve the hardware reduction, it is designed that a multifunctional BILBO has double operational functions of NLFSR and LFSR, when neccessary, and that test signal could be used as an input-output signal in the same line. By applying the proposed multifunctional BILBO to the sequential PLA, the test patterns and the additional circuit could be reduced in test operation and the propagation delay is vanished in normal operation, as we expected. Above them, the partitioned method for large scale sequential circuit is also suggested and it is observed that test patterns and additional circuit in them reduced by this method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.8
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• pp.475-481
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• 2005

In the existing ICT technique, the mounted electronic devices on the printed circuit board are tested whether the devices are good or not by comparing and measuring the value of the devices after separating the devices to be tested from around it based on the guarding method. But, in case that resistance, inductor and capacitor are configured as a parallel circuit on the circuit pattern, values for each device can not be measured because the total impedance value of the parallel circuit is measured. Accordingly, it is impossible to test whether the parallel circuit is good or not in case that the measured impedance value is within the tolerance error. Also, it is difficult to identify that which device among R, L and C of the parallel circuit is bad in case that the measured impedance value is out of the tolerance error. Accordingly, this paper proposes a test method which can enhance the quality and productivity by separating and measuring accurately R, L and C components from the RLC parallel circuits on the device-mounted printed circuit board. First, the RLC parallel circuit to be test is separated electrically from around it using three-terminal guarding technique. And then R, L and C values are computed based on the total impedance values and phase angles between voltage and current of the parallel circuit measured from two AC input signals with other frequency, Finally, the availability and accuracy of the proposed test method is verified by reviewing the simulation results.