• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.5
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• pp.32-44
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• 1997

A three-dimensional (3D) full-dynamic damage model for ion implantation in crystalline silicon was proposed to calculate more accurately point defect distributions and ion-implanted concentration profiles during ion implantation process. The developed model was based on the physical monte carlo approach. This model was applied to simulate B and BF2 implantation. We compared our results for damage distributions with those of the analytical kinchin-pease approach. In our result, the point defect distributions obtained by our new model are less than those of kinchin-pease approach, and the vacancy distributions differ from the interstitial distributions. The vacancy concentrations are higher than the interstitial ones before 0.8 . Rp to the silicon surface, and after the 0.8 . Rp to the silicon bulk, the interstitial concentrations are revesrsely higher than the vacancy ones.The fully-dynamic damage model for the accumulative damage during ion implantation follows all of the trajectories of both ions and recoiled silicons and, concurrently, the cumulative damage effect on the ions and the recoiled silicons are considered dynamically by introducing the distributon probability of the point defect. In addition, the self-annealing effect of the vacancy-interstitial recombination during ion implantation at room temperature is considered, which resulted in the saturation level for the damage distribution.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.946-949
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• 1999

In this research we have developed a reliable, effective and feasible HEI(High-Energy Ion Implantation) process 3D-simulation tool, and then by using it we can predict and analyze the effect of HEI process on characteristics of the standard CMOS device. high-energy ion implantation above 200 keV is inevitable process to form retrograde well and buried layer to prevent leakage current, to conduct field implant for field isolation, and to perform after-gate implantation. The feasible analysis tool is a product of the HEI process modeling verified by comparison of the SIMS experiments with the simulation results. Especially, in this paper, we present the predicting capability of HEI-induced impurity and damage profiles compared with the published SIMS data in order to acquire the reliability of our results ranging from few keV to several MeV for phosphorus and boron implantation.

• Journal of the Korean Vacuum Society
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• v.2 no.4
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• pp.468-473
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• 1993

Damages on Si substrate induced by Ar ion implantation and it annealing behavior during rapid thermal annealing were investigated by the cross-sectional TEM (transmissin electron microscopy), RB(Rutherfordbackscattering) spectra an dthermal wave (TW) modulation reflectance methods. Continuous amorphous layer extending to the surface were generated by Ar ion implantation for higher doses than 1 $\times$1015cm-2. The recrystallization of the amorphous layer prodeeded as the annealing temperature increased . However the amorphous /crystal interfacial undulations caused the micro twins and damage clusters. Damage clusters generated by lower doses than 1 $\times$1015 cm-2 disappeared slowly as the annealing temperature increased, but even at 110$0^{\circ}C$ a few damage clusters still remained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.346-349
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• 2002

High Power and high dose ion implantation is essentially needed to make power MOSFET devices based on SiC wafers, because the diffusivities of the impurities such as Al, N, p, B in SiC crystal are very low. In addition, it is needed high temperature annealing for electrical activation of the implanted species. Due to the very high annealing temperature, the surface morphology after electrical activation annealing becomes very rough. We have found the different surface morphologies between implanted and unimplanted region. The unimplanted region showed smoother surface morphology It implies that the damage induced by high energy ion implantation affects the roughening mechanism. Some parts of Si-C bonding are broken in the damaged layer, s\ulcorner the surface migration and sublimation become easy. Therefore the macrostep formation will be promoted. N-type 4H-SiC wafers, which were Al ion implanted at acceleration energy ranged from 30kev to 360kev, were activated at 1600$^{\circ}C$ for 30min. The pre-activation annealing for damage relaxation was performed at 1100-1500$^{\circ}C$ for 30min. The surface morphologies of pre-activation annealed and activation annealed were characterized by atomic force microscopy(AFM).

• Journal of the Korean Society for Heat Treatment
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• v.13 no.4
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• pp.259-264
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• 2000

In this study, we quantitatively measure the ion ranges of arsenic with energies ranging from 10 KeV to 100 KeV, implanted at $3^{\circ}$, $9^{\circ}$ $15^{\circ}$ the (100) plane, and the damage created during ion implantation. To obtain detailed information of ion range and damage distributions in low energy region where elastic collisions dominate the slowing down process, molecular dynamics computer simulation was performed and compared to the existing results. The effects of implant energy and degree on damage generation are present. The number of vacancy were calculated from the deposited energy using Kinchin-Pease equation. In the energy range 10 keV-100 keV, simulations show that the number of Frenckel pairs produced by As-ion bimbardment is 9 and incident angle dependence of the vacancy was the same but defects were distributed at different depth.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.91-99
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• 1994

Damage induced by Si ion implantation and its annealing behavior during rapid thermal annealing were investigated by cross-sectional TEM (transmission electron microscopy) and RB ( Rutherford backscattering) spectrum. 150keV and 50keV Si ions were implanted in Si (100) at room temperature with doses of 2${\times}10^{15}cm^{-2}$. And 100keV Si ions were implanted in Si with doses from 1${\times}10^{14}cm^{-2}$. A variety of damage structures were generated by Si ion implantation such as continuous amorphous layer extending to the surface buried amorphous layer and damage clusters. Damage clusters are annealed out at the lower annealing temperature of 550 $^{\circ}C$. However, event at the temperature of 110$0^{\circ}C$ end of range loops remain in the original lower amorphous/crystal interface in the case of continuous and buried amorphous layer formation. Extended defects in the shape of zipper dislocations are also observed at the middle of the recrystallized region in the buried amorphous layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.8
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• pp.609-615
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• 2011

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.6-6
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• 2009

We present an alternative process whereby deuterium is delivered to the location where the gate oxide reside by an implantation process. Deuterium ions were implanted using different energies to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas was performed to remove the D-implantation damage. We have observed that deuterium ion implantation into the gate oxide region can successfully remove the interface states and the bulk defects.

• Journal of Korean Vacuum Science & Technology
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• v.1 no.1
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• pp.1-12
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• 1997

A new three-dimensional (3D) Monte Carlo ion implantation simulator, TRICSI, has been developed to investigate 3D mask effects in the typical mask structure for ion implantation into crystalline silicon. We present the mask corner and mask size effects of implanted boron range profiles, and also show the calculated damage distributions by applying the modified Kinchin-Pease equation in the single-crystal silicon target. The simulator calculates accurately and efficiently the implanted-boron range profiles under the relatively large implanted area, using a newly developed search algorithm for the collision partner in the single-crystal silicon. All of the typical implant parameters such as dose, tilt and rotation angles, in addition to energy can be used for the 3D simulation of ion implantation.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.