• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.89-101
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• 2005

Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• 전기학회논문지
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• 제60권1호
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제11권5호
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• pp.133-138
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• 2022

최근 고성능컴퓨팅, 인공지능 분야에서 GPU 장치 사용이 일반화되고 있지만, GPU 프로그래밍은 여전히 어렵게 여겨진다. 특히 호스트(host) 메모리와 GPU 메모리를 별도로 관리하기 때문에 성능과 편의성 방면에서 연구가 활발히 진행되고 있다. 이에 따라 여려가지 CPU-GPU 메모리 전송 방법들이 연구되고 있다. 한편 CPU와 GPU 및 통합메모리(Unified memory) 등 하나의 실리콘 패키지로 묶는 SoC(System on a Chip) 제품들이 최근에 많이 출시되고 있다. 본 연구는 이러한 통합메모리 장치에서 CPU, GPU 장치간 데이터를 사용하고 전송시 성능관련 비교를 하고자 한다. 기존 CPU내 호스트 메모리와 GPU 메모리가 분리된 환경과는 다른 특징을 보여준다. 여기서는 통합메모리 장치인 NVIDIA SoC칩들과 NVIDIA SMX 기반 V100 GPU 카드에서 CPU-GPU 간 데이터 전송 프로그래밍 기법별로 성능비교를 한다. 성능비교를 위해 워크로드는 HPC 분야의 수치계산에서 자주 사용하는 2차원 행렬 전치 커널이다. 실험을 통해 CPU-GPU 메모리 전송 프로그래밍 방법별 GPU 커널 성능차이, 페이지 잠긴 메모리와 페이지 가능 메모리를 사용했을 경우 전송 성능차이, 전체(Overall) 성능비교, 마지막으로 워크로드 크기별 성능비교를 하였다. 이를 통해 통합메모리칩인 NVIDIA Xavier에서 I/O 캐시일관성 지원을 통해 SoC 칩내 통합메모리에 대한 이점을 극대화 할 수 있음을 확인할 수 있었다.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2014년도 제49차 동계학술대회논문집 22권1호
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• pp.9-13
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• 2014

The performance of large scale software applications has been automatically increasing for last few decades under the influence of Moore's law - the number of transistors on a microprocessor roughly doubled every eighteen months. However, on-chip transistors limitations and heating issues led to the emergence of multicore processors. The energy efficient ARM based System-on-Chip (SoC) processors are being considered for future high performance computing systems. In this paper, we present a case study of two widely used parallel programming models i.e. MPI and MapReduce on distributed memory cluster of ARM SoC development boards. The case study application, Black-Scholes option pricing equation, was parallelized and evaluated in terms of power consumption and throughput. The results show that the Hadoop implementation has low instantaneous power consumption that of MPI, but MPI outperforms Hadoop implementation by a factor of 1.46 in terms of total power consumption to execution time ratio.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• 대한전자공학회논문지SD
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• 제43권6호
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• pp.9-17
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• 2006

SoC(System-On-Chip) 시스템에서 초 저전력 시스템을 구현하기 위한 dynamic voltage and frequency scaling (DVFS)알고리즘에 사용될 시스템 버스의 다중 코어 전압 레벨을 생성해주는 새로운 다계층(multi-level) 코어 전압용 high-speed level up/down Shifter 회로를 제안한다. 이 회로는 내부 회로군과 외부 회로군 사이에서 서로 다른 전압레벨을 조정 접속하는 I/O용 level up/down shifter interface 회로로도 동시에 사용된다. 제안하는 회로는 인터페이스 접속에서 불가피하게 발생하는 속도감쇄와 Duty Ratio 불안정 문제를 최소화하는 장점을 갖고 있다. 본 회로는 500MHz의 입력 주파수에서 $0.6V\sim1.6V$의 다중 코어 전압을 각 IP들에서 사용되는 전압레벨로, 또는 그 반대의 동작으로 서로 Up/Down 하도록 설계하였다 그리고 제안하는 I/O 용 회로의 level up shifter는 500MHz의 입력 주파수에서 내부 코어 용 level up shifter의 출력전압인 1.6V를 I/O 전압인 1.8V, 2.5V, 3.3V로 전압레벨을 상승 하도록 설계하였으며, level down shifter는 반대의 동작으로 1Ghz의 입력 주파수에서 동작하도록 설계하였다. 시뮬레이션 및 결과는 $0.35{\mu}m$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process 와 65nm CMOS model 변수를 이용한 Hspice를 통하여 검증하였다. 또한, 제안하는 회로의 지연시간 및 파워소모 분석과 동작 주파수에 비례한 출력 전압의 Duty ratio 왜곡에 대한 연구도 하였다.

• 한국콘텐츠학회논문지
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• 제8권3호
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• pp.25-31
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• 2008

본 논문은 다중전원공급 SoC(System-on-Chip)에 사용될 저전력 단일전원 level-up/down shifter를 제안한다. 제안된 회로는 다양한 전원을 사용하는 IP간의 신호의 인터페이스 회로로 사용할 수 있으며, 단일전원을 사용함으로써 저전력으로 동작하고 시스템의 전원배선과 레이아웃의 복잡도 및 지연시간이 감소하는 장점을 가지고 있다. 제안된 level-up/down shifter는 각각 IP간에 신호들이 level-up 일 때는 500MHz 입력 주파수에서 동작하고 level-down일 때는 1GHz에서 동작하도록 설계했다. I/O 회로에 level-up/down shifter를 사용하면 시스템간의 신호를 연결할 때 잡음에 강하다는 사실도 검증했다. 시뮬레이션 결과는 0.18um CMOS 공정에서 각각 1.8V, 2.5V, 3.3V의 전원을 사용하여 검증했다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• 디지털산업정보학회논문지
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• 제18권4호
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• pp.47-54
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• 2022

In this paper, MEMS embedded system design implemented the sensor events via analyzing the characteristics that dynamically happened to an abnormal status in power IoT environments in order to guarantee a maintainable operation. We used three kinds of tools in this paper, at first Bluetooth Low Energy (BLE) technology which is a suitable protocol that provides a low data rate, low power consumption, and low-cost sensor applications. Secondly LSM6DSOX, a system-in-module containing a 3-axis digital accelerometer and gyroscope with low-power features for optimal motion. Thirdly BM1422AGMV Digital Magnetometer IC, a 3-axis magnetic sensor with an I2C interface and a magnetic measurable range of ±120 uT, which incorporates magneto-impedance elements to detect the magnetic field when the current flowed in the power devices. The proposed MEMS system was developed based on an nRF5340 System on Chip (SoC), previously compared to the standalone embedded system without bluetooth technology via mobile App. And also, MEMS embedded system with BLE 5.0 technology broadcasted the MEMS system status to Android mobile server. The experiment results enhanced the performance of MEMS system design by combination of sensors, BLE technology and mobile application.