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ViP: A Practical Approach to Platform-based System Modeling Methodology  

Um, Jun-Hyung (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Hong, Sung-Pack (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Kim, Young-Taek (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Chung, Eui-Young (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Choi, Kyu-Myung (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Kong, Jeong-Taek (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Eo, Soo-Kwan (CAE Center, SoC R&D, System LSI Div. Samsung Electronics)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.5, no.2, 2005 , pp. 89-101 More about this Journal
Abstract
Research on highly abstracted system modeling and simulation has received a great deal of attention as of the concept of platform based design is becoming ubiquitous. From a practical design point of view, such modeling and simulation must consider the following: (i) fast simulation speed and cycle accuracy, (ii) early availability for early stage software development, (iii) inter-operability with external tools for software development, and (iv) reusability of the models. Unfortunately, however, all of the previous works only partially addresses the requirements, due to the inherent conflicts among the requirements. The objective of this study is to develop a new system design methodology to effectively address the requirements mentioned above. We propose a new transaction-level system modeling methodology, called ViP (Virtual Platform). We propose a two-step approach in the ViP method. In phase 1, we create a ViP for early stage software development (before RTL freeze). The ViP created in this step provides high speed simulation, lower cycle accuracy with only minor modeling effort.(satisfying (ii)). In phase 2, we refine the ViP to increase the cycle accuracy for system performance analysis and software optimization (satisfying (i)). We also propose a systematic ViP modeling flow and unified interface scheme based on utilities developed for maximizing reusability and productivity (satisfying (ii) and (iv)) and finally, we demonstrate VChannel, a generic scheme to provide a connection between the ViP and the host-resident application software (satisfying (iii)). ViP had been applied to several System-on-a-chip (SoC) designs including mobile applications, enabling engineers to improve performance while reducing the software development time by 30% compared to traditional methods.
Keywords
System on Chip; Platform-based design; Transaction-level modeling;
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