• Journal of Internet Computing and Services
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• v.7 no.6
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• pp.105-112
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• 2006

This paper be composed to file system by making a new i_node structure which can decrease Write frequency because this's can improved the file system efficiency if reduced Write operation frequency of flash memory in respect of file system, i-node is designed to realize Cleaning policy of data in order to perform Write operation. This paper suggest Cleaning Algorithm for Write operation through a new i_node structure. In addition, this paper have mode the oldest data cleaned and the most recent data maintained longest as a result of experiment that the recent applied program and data tend to be implemented again through the concept of regional and time space which appears automatically when applied program is implemented. Through experiment and realization of the Flash file system, this paper proved the efficiency of NAND-type flash file system which is required in on Embedded system.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.1-10
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• 2011

There are the large overhead of block erase and page write operations in NAND flash memory, though it has low power consumption, cheap prices and a large storage. Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, so rewriting operation require after erase operation. it cause performance decrease of NAND flash memory. Using SRAM buffer in traditional NAND flash memory, it can not only reduce effective write operation but also guarantee fast memory access time. In this paper, we proposed the small SRAM buffer management system for reducing overhead of NAND flash memory, that is, erase and write operations. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer with the small fetching block size and a fully associative spatial buffer with the large fetching block size. The temporal buffer have small fetching blocks that referenced from spatial buffer. When it happen write operations or erase operations in NAND flash memory, the related fetching blocks in temporal buffer include a page or a block are written in NAND flash memory at the same time. The writing and erasing counts in NAND flash memory can be reduced. According to the simulation results, although we have high miss ratios, write and erase operations can be reduced approximatively 58% and 83% respectively. Also the average memory access times are improved about 84% compared with the fully associative buffer with two sizes.

• The Journal of the Korea Contents Association
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• v.16 no.8
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• pp.706-716
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• 2016

Because of efficient space utilization and fast key search times, B-trees have been widely accepted for the use of indexes in HDD-based DBMSs. However, when the B-ree is stored in flash memory, its costly operations of node updates may impair the performance of a DBMS. This is because the random updates in B-tree's leaf nodes could tremendously enlarge I/O costs for the garbage collecting actions of flash storage. To solve the problem, we make all the parents of leaf nodes the virtual nodes, which are not stored physically. Rather than, those nodes are dynamically generated and buffered by referring to their child nodes, at their access times during key searching. By performing node updates and tree reconstruction within a single flash block, our proposed B-tree can reduce the I/O costs for garbage collection and update operations in flash. Moreover, our scheme provides the better performance of key searches, compared with earlier flash-based B-trees. Through a mathematical performance model, we verify the performance advantages of the proposed flash B-tree.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.77-88
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• 2009

According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)'s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.

• Corrosion Science and Technology
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• v.22 no.5
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• pp.341-350
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• 2023

In the present study, effects of a thin Zn-flash coating on hydrogen evolution, infusion, and embrittlement of advanced high strength steel during electro-galvanizing were examined. The electrochemical permeation technique in conjunction with impedance spectroscopy was employed under applied cathodic polarization. Moreover, a slow-strain rate test was conducted to evaluate loss of elongation (i.e., indicative of hydrogen embrittlement (HE)) and examine fracture surfaces. Results showed that the presence of a thin Zn-flash coating, even when it was not distributed uniformly, reduced hydrogen evolution rate and substantially impeded infusion of hydrogen into the steel substrate. This was primarily due to a hydrogen overvoltage on Zn coating and trapping of hydrogen at the interface of Zn coating/flash coating/steel substrate. Consequently, the sample with flash coating had a smaller HE index than the sample without flash coating. These results suggest that a thin Zn-flash coating could be an effective technical strategy for mitigating HE in advanced high-strength steels.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.11
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• pp.379-384
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• 2016

NAND flash storage is widely used for computer systems, because of it has faster response time, lower power consumption, and larger capacity per unit area than hard disk. However, currently used I/O scheduler in the operating system is optimized for characteristics of the hard disk. Therefore, the conventional I/O scheduler includes the unnecessary overhead in the case of the NAND flash storage to be applied. Particularly, when the write requests performed intensively, garbage collection is performed intensively. So, it occurs the problem that the processing of the I/O request delay. In this paper, we propose the new I/O scheduler to solve the problem of garbage collection performs intensively, and to optimize for NAND flash storage. In the result of performance evaluation, proposed scheme shows an improvement the user responsiveness by reducing 1% of the average read response time and 78% of the maximum response time.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.2
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• pp.201-205
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• 2008

The flash memory is widely used as a main storage of embedded devices. It is adopted as a storage of database as growing the capacity of the flash memory. We run TPC-C benchmark on various FTL algorithms. But, the database shows poor performance on flash memory because the characteristic of I/O requests is full random. In this paper, we show the performance of all existing FTL algorithms is very poor. Especially, the FTL algorithm known as good at small mobile equipment shows worst performance. In addition, the chip-inter leaving which is a technique to improve the performance of the flash memory doesn't work well. In this paper, we inform you the reason that we need a new FTL algorithm and the direction for the database in the future.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.177-185
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• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.51 no.spc1
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• pp.166-173
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• 2006

Soyasaponins are phytochemicals of major interest fur their health benefits. Chemical investigation of a soybean phytochemical concentrate resulted in the isolation and identification of triterpenoid saponins. The MeOH extraction of defatted hypocotyl separated from soybeans was peformed by the automated solvent extractor (ASE). Fractionation was performed on a flash column ($150mm{\times}40mm$ i.d.) packed with a preparative $C_{18}$ reverse phase bulk packing material $(125\AA,\;55-105{\mu}m)$ and monitored at 210 nm, and collected 14 fractions. Consequent Fsat preparative column liquid chromatography (Fast PCLC) was performed for the purification of Fraction-I (Fr-I) collected from the fraction 8 and 9 of flash chromatography. Fsat PCLC was performed on a Luna $C_{18}\;10{\mu}m,\;100{\AA}$, semipreparative reverse phase column ($250cm{\times}50mm$ i.d.) for the purification of isolated unknown compound (Fr-I-2). Chemical structure of acetyl soyasaponin $A_1\;(MW:1436.6,\;C_{67}H_{104}O_{33})$ was identified and determined by a combination of extensive NMR ($^1H-NMR$, 400 MHz; $^{13}C-NMR$, 100 MHz; DEPT), IR, UV, and ESI-MS analysis.