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Efficient Prefetching and Asynchronous Writing for Flash Memory  

Park, Kwang-Hee (인하대학교 전자공학과)
Kim, Deok-Hwan (인하대학교 전자공학과)
Publication Information
Journal of KIISE:Computing Practices and Letters / v.15, no.2, 2009 , pp. 77-88 More about this Journal
Abstract
According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)'s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.
Keywords
FTL; Clustered hash table; Prefetch; 2-bit write prediction;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 Intel Corporation, “Understanding the Flash Trans-lation Layer (FTL) Specification,” 1998
2 Ban, A. 1995. Flash file system. US patent 5,404,485. Filed March 8, 1993; Issued April 4, 1995; Assigned to M-Systems
3 M. Talluri, M. D. Hill and Y. A. Khalidi, “A new Page Table for 64-bit address spaces,” Procee-dings of the 15th ACM Symposium on Operating Systems Principles, Dec 1995   DOI
4 K-H. Park and D-H. Kim, “A Clustered Flash Translation Layer for CompactFlash Systems,” IEEE international Conference on Consumer Elec-tronics, Las Vegas, NV, U. S. A., Jan. 2008   DOI
5 Intel Corporation, "Software Concerns of Imple-menting a Resident Flash Disk," 1995
6 Ban, A. 1999, Flash file system optimized for page-mode flash technologies. US patent 5,937,425. Filed October 16, 1997; Issued August 10, 1999; Assigned to M-Systems
7 A. Silberschatz, P. B. Galvin, and G. Gagne, "Operating System Concepts, 7th Edition," John Wiley & Sons, Inc., pp. 315-326, 2005
8 Samsung Electronics, 'K9F1208U0C,' Data Sheet of NAND Flash Memory
9 C-H. Wu and T-W. Kuo, "An Adaptive Two- Level Management for the Flash Translation Layer in Embedded Systems," IEEE/ACM Inter-national Conference on Computer Aided Design, San Jose, CA, Nov. 2006   DOI
10 MTD, "Memory Technology Device (MTD) subsys-tem for Linux," http://www.linux-mtd.infradead.org
11 E. Gal, S. Toledo, “Algorithm and Data Structure for Flash Memories,” ACM Computing Surveys, Vol.37, Issue 2, pp. 138-163, 2005   DOI   ScienceOn
12 Samsung Electronics, “K9K8G08U1A,” Data Sheet of NAND Flash Memory
13 Gartner Dataquest, “Forecast: Memory, Worldwide, 2001 -2011(3Q07 Update),” Nov. 2007
14 John L. Hennessy and David A. Patterson, "Com-puter Architecture: A Quantitative Approach 3/E," Morgan Kaufmann Publishers
15 이종민, 김성훈, 안성준, 이동희, 노삼혁, "NAND 플래시 메모리 저장장치에서 블록 재활용 기법의 비용 기반 최적화", 정보과학회논문지: 컴퓨팅의 실제 및 레터 제13권 7호, pp. 508-519, 2007년 12월   과학기술학회마을
16 J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, “A space-efficient flash translation layer for CompactFlash systems,” IEEE Transaction on Consumer Electronics, Vol.48, No.2, pp 366-375, 2002   DOI   ScienceOn
17 S. W. Lee, W. K. Choi, D. J. Park, "FAST: An Efficient Flash Translation Layer for Flash Memory," EUC 2006 Workshops, Lecture Notes in Computer Science, No.4097 pp 879-887, Aug. 2006   DOI
18 Ban, A. 2004. Wear leveling of static areas in flash memory. US patent 6,732,221. Filed June 1, 2001; issued May 4, 2004; Assigned to M-Sys-tems