• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.201-206
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• 2015

A new electronically stopband tunable filter is proposed with three-input single-output using Operational Transconductance Amplifier (OTA) in this paper. The proposed filter provides band pass, low pass and high pass multifunctional responses. Centre frequency ($f_c$) and quality factor (Q) of the realized filters could independently tuned without disturbing each other. Various network sensitivity and non-ideal characteristic analysis are done to check the sensitivity and parasitic effect of different circuit parameters. The CMOS realization of filter is done with 1.8V-0.18um process parameters and HSPICE simulation results are presented to assert the presented theory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.500-505
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed frequency divider has designed in a standard 0.25$\mu\textrm{m}$ CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65$\mu\textrm{m}$ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz, a tuning range of ${\pm}$10%, and a gain of 154MHz/V. The simulated frequency synthesizer performance has a settling time of 1.5${\mu}\textrm{s}$, a frequency range from 820MHz to 1GHz and power consumption of 70mW at 2.5V power supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.40-47
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• 2009

In this paper, we present the design of a source driver of QVGA scale TFT-LCD driver IC which uses a mixed driving method and performs $\gamma$-correction to improve image. The source driver with 240 RGB ${\times}$ 320 dots resolution drives a TFT-LCD panel through 720 channels and implements 262k colors using 18-bit RGB data format. The mixed driving method is a mixture the channel amp. driving method with high drivability and the gray amp. driving method with small area, which remarkably reduces channel driver areas. The driver has been designed using the $0.35{\mu}m$ Magnachip embedded DRAM technology and simulated using the HSPICE simulator. The results show that our source driver operates well with y-correction and the channel driver has $17{\mu}s$ channel driving time with only 78 driving amplifiers and control logic.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• Journal of IKEEE
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• v.12 no.1
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• pp.1-7
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• 2008

With the recent development of portable system such as mobile communication and multimedia. Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional Ratioed logic and Pass Transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. Layouts have been carried out using a 0.18um CMOS design rule for evaluation purposes. The physical design has been evaluated using HSPICE.

• Journal of IKEEE
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• v.22 no.2
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• pp.420-426
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• 2018

In the near future, CNTFET(Carbon NanoTube Field Effect Transistor) is considered as one of the most promising candidate for the replacement of modern silicon-based transistors by utilizing the ballistic or near-ballistic transport capability of CNT(Carbon NanoTube). For the large-scale fabrication of high performance CNTFET, semiconducting CNTs have to be well-aligned with a fixed pitch and high densities in the each CNTFET. However, due to the immaturity of the CNTFET fabrication process, CNTs can be unevenly positioned in a CNTFET and existing HSPICE library file cannot support the circuit level evaluation of performance variation caused by the unevenly positioned CNTs. To evaluate the performance variation, linear programming methodology was suggested previously, but the errors can be made during the calculation of the current and the gate capacitance of a CNTFET. In this paper, the reasons causing errors will be discussed in detail and the new methodology to reduce the errors will be also suggested. Simulation results shows that the errors can be reduced from 7.096% to 3.15%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.13-22
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• 1998

In this paper, we propose a high-performance BICS(built-in current sensor) which is fabricated in 0.8${\mu}{\textrm}{m}$ single-poly two-metal process for IDDQ testing of CMOS VLSI circuit. The CUT(circuit under test) is 4-bit full adder with a bridging fault. Using two nMOSs that have different size, two bridging faults that have different resistance values are injected in the CUT. And controlling a gate node, we experimented various fault effects. The proposed BICS detects the faulty current at the end of the clock period, therefore it can test a CUT that has a much longer critical propagation delay time and larger area than conventional BICSs. As expected in the HSPICE simulation, experimental results of fabricated chip demonstrated that the proposed BICS can exactly detect bridging faults in the circuit.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.29-34
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• 1999

In this paper, a current comparative frequency automatic tuning circuit for the CMOS gm-C bandpass filters are designed with the new architecture. And also, when the designed circuit is compared to the typical tuning circuit, the designed circuit has very simple architecture that is composed of the current comparator and charge pump and operating in 3V power supply. The proposed tuning circuit automatically compensates the difference between the operating current of the transconductor and the specified reference Current. Using CMOS 0.8um parameter a biquad gm-C bandpass filter with center frequency($f_\circ$=60MHz) is designed, and according to the transistor size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operation of the proposed current comparative frequency automatic tuning circuit is verified.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.49-57
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• 2001

In this paper, equivalent circuit model and novel model parameter extraction method of a silicon(Si) substrate are presented. Substrate coupling through Si-substrate is quantitatively investigated by analyzing equivalent circuit with operating frequency and characteristic frequencies (i.e., pole and zero frequency) of a system. For the experimental verification of the equivalent circuit and parameter extraction method, test patterns are designed and fabricated in standard CMOS technology with various isolation distances, substrate resistivity, and guard-ring structures. Then, these are measured in l00MHz-20GHz frequency range by using vector network analyzer. It is shown that the equivalent-circuit-based HSPICE simulation results using extracted parameters have excellent agreement with the experimental results. Thus, the proposed equivalent circuit and parameter extraction methodology can be usefully employed in mixed-signal circuit design and verification of a circuit performance.