• Title/Summary/Keyword: high-speed circuits

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Design of a Built-In Current Sensor for CMOS IC Testing (CMOS 집적회로의 테스팅을 위한 새로운 내장형 전류감지 회로의 설계)

  • Hong, Seung-Ho;Kim, Jeong-Beom
    • Proceedings of the KIEE Conference
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    • 2003.11b
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    • pp.271-274
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    • 2003
  • This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

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Design and Measurements of an RSFQ NDRO circuit (단자속 양자 NDRO 회로의 설계와 측정)

  • 정구락;홍희송;박종혁;임해용;강준희;한택상
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2003.10a
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    • pp.76-78
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    • 2003
  • We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25%. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15%. The circuit was measured at the liquid helium temperature.

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PCB Defects Detection using Connected Component Classification (연결 성분 분류를 이용한 PCB 결함 검출)

  • Jung, Min-Chul
    • Journal of the Semiconductor & Display Technology
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    • v.10 no.1
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    • pp.113-118
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    • 2011
  • This paper proposes computer visual inspection algorithms for PCB defects which are found in a manufacturing process. The proposed method can detect open circuit and short circuit on bare PCB without using any reference images. It performs adaptive threshold processing for the ROI (Region of Interest) of a target image, median filtering to remove noises, and then analyzes connected components of the binary image. In this paper, the connected components of circuit pattern are defined as 6 types. The proposed method classifies the connected components of the target image into 6 types, and determines an unclassified component as a defect of the circuit. The analysis of the original target image detects open circuits, while the analysis of the complement image finds short circuits. The machine vision inspection system is implemented using C language in an embedded Linux system for a high-speed real-time image processing. Experiment results show that the proposed algorithms are quite successful.

Double Gate MOSFET Modeling Based on Adaptive Neuro-Fuzzy Inference System for Nanoscale Circuit Simulation

  • Hayati, Mohsen;Seifi, Majid;Rezaei, Abbas
    • ETRI Journal
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    • v.32 no.4
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    • pp.530-539
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    • 2010
  • As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro-fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics-based models, like non-equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.

Temperature dependency of dc Characteristics for HEMTs (온도변화에 따른 HEMT의 DC 특성 연구)

  • 김진욱;황광철;이동균;안형근;한득영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.29-32
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    • 2000
  • In this paper, an analytical model for I-V characteristics of a HEMTs is Proposed. The developed model takes into account the temperature dependence of drain current. In high-speed ICs for optical communication systems and mobile communication systems, temperature variation affects performance; for example the gain, efficiency in analog circuits and the delay time, power consumption and noise mrgin in digital circuits. To design such a circuit taking into account the temperature dependence of the current-voltage characteristic is indispensible. This model based on the analytical relation between surface carrier density and Fermi potential including temperature dependent coefficients.

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Protection relaying algorithm for DFIG using a DQ equivalent circuit (DQ 등가회로를 이용한 DFIG 보호계전방식)

  • Kang, Yong-Cheol;Lee, Ji-Hoon;Jang, Sung-Il;Kim, Yong-Gyun
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.23-24
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    • 2007
  • Most of modern wind turbines employs a doubly-fed induction generator (DFIG) system because it has many advantages due to variable-speed operation, relatively high efficiency and it small converter size. The DFIG system uses a wound rotor induction machine so that the magnetizing current of the generator can be fed from both the stator and the rotor. This paper presents a protection relaying algorism for DFIG using the DQ equivalent circuits. The induced voltages calculated from the stator and rotor sides are nearly the same in the steady state. They become different in the DQ equivalent circuits during an internal fault. The proposed algorithm compares the inducted voltages estimated from the stator and the rotor circuit converted into the stationary reference frame. If the difference between the induced voltages exceeds the threshold, the proposed algorithm detects an turn-to-turn fault.

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A design of Adaptive Decision-feedback Equalizer Module using Redundant Binary Complex Filter (Redundant Binary 복소수 필터를 이용한 적응 결정귀환 등화기 모듈 설계)

  • 김호하;안병규신경욱
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.1125-1128
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    • 1998
  • A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.

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Design and Analysis of Thrust Magnetic Bearing/Damper for 300HP Class High Speed Motor (300마력급 초고속 전동기의 스러스트 자기 베어링/댐퍼 설계 및 특성해석)

  • Jang, Seok-Myeong;Choi, Jang-Young;Park, Ji-Hoon;Lee, Yong-Bok;Lee, Hee-Sub
    • Proceedings of the KIEE Conference
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    • 2007.04c
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    • pp.5-7
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    • 2007
  • This paper deals with design and analysis of thrust magnetic bearing for 300HP class high speed motor. Using the solutions obtained from equivalent magnetic circuits, we predicts the electromagnetic characteristics such as thrust, time constant and power loss according to design parameters. And then, using non-linear finite element analysis, a detailed design is performed considering saturation in order to meet requirements.

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A Plated Through Hole Model and A Connector Model for HSPICE (HSPICE용 plated through hole (PTH) 모형과 커넥터 모형)

  • 이명호;전용일;전병윤;박권철;강석열
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.7
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    • pp.63-71
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    • 1998
  • Generally, electronic packaging designer uses HSPICE SOFTWARE TOOL to validate electric characteristics of traces layout before layout traces in PCB in hundreds Mb/s high speed digital circuits. We are in need of a plated through hole (PTH) model and a connector model to use HSPICE SOFTWARE TOOL. Those models have not been perfectly defined for HSPICE simulation. In this paper, we define a PTH model and a connector model for HSPICE simulation and discuss application range for these models. Th emodels are analytic models very applicable for HSPICE simulation and are used to analyze electric characteristic of the PTH and the connector in thetraces layout in high speed digital circuit.

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Optimization of the Thermal Behavior of Linear Motors with High Speed and Force ($2^{nd}$ Paper) (고속.대추력 리니어모터의 열특성 최적화 [2])

  • Eun, In-Ung
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.7
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    • pp.163-170
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    • 2002
  • This paper presents some measures far the optimization of the thermal behavior of linear motors, which are used as a high speed feed mechanism in machine tools. Thermo-Sandwich-Construction using two cooling circuits and an insulation layer shows an effective cooling system for linear motors. Conducting sheet can be also used to reduce heat flow from linear motor to machine table. Cooling pipe is a simple and effective cooling system for the secondary part of synchronous linear motor. Through the combination of the Thermo-Sandwich-Construction, conducting sheet and cooling pipe the thermally optimized linear motor shows a well improved thermal behavior in comparison with the prototype motor.