• Journal of IKEEE
• /
• v.19 no.4
• /
• pp.520-525
• /
• 2015

This paper investigates the consensus problem for high-order integrators with an arbitrary large communication delay. In order to solve this problem, new consensus controller with an additional design parameter that can eliminate the effect of a communication delay on the consensus problem is proposed. Also, it is proved that the proposed consensus controller can always solve the consensus problem of high-order integrators even in the presence of an arbitrarily large communication delay. Finally, an illustrative example is given in order to show the effectiveness of our design method.

• Journal of IKEEE
• /
• v.20 no.4
• /
• pp.378-384
• /
• 2016

This paper addresses the output feedback consensus problem for high-order integrators under a directed network with a communication delay. In order to solve this problem, the dynamic output feedback controller is proposed. Also, by using Lyapunov-Krasovskii functional, it is shown that the existence of the proposed consensus controller can always be guaranteed even in the presence of an arbitrarily large communication delay.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.6
• /
• pp.1081-1086
• /
• 2008

This paper presents the $3^{rd}$ 4bit sigma delta modulator with the block and timing diagrams of DWA(Data Weighted Averaging) to optimize a operating time. In the modulator, the proposed DWA structure has a stable operation and timing margin so as to remove three latches and another clock. Because the modulator with proposed DWA structure improve timing margin about 23%. It can increase sampling frequency up to 244MHz. Through the MATLAB modeling, the optimized coefficients are obtained to design the modulator. The fully differential SC integrators, DAC, switch, quantizer, and DWA are designed by considering the nonideal characteristics. The designed $3^{rd}$ order 4bit modulator has a power consumption of 40mW and SNR(signal to noise ratio) of 77.2dB under 1.2V supply and 64MHz sampling frequency.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.361-364
• /
• 2003

In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.

• Proceedings of the KIPE Conference
• /
• 2017.11a
• /
• pp.63-64
• /
• 2017

This paper proposes a speed estimator for sensorless control of diesel-generator (genset) systems, where the speed of the genset is calculated from the back-EMF frequency of the generator. The back-EMF frequency is extracted from a phase output current by using multiple second-order generalized integrators (SOGIs) connected in parallel and series and separated frequency-locked loops. The proposed method (PS-SOGI-FLL) is able to estimate the fundamental frequency in the distorted output current with high accuracy and strong robustness. Simulation results are shown to verify the validity of the proposed method.

• Journal of the Korean Magnetics Society
• /
• v.15 no.4
• /
• pp.250-255
• /
• 2005

A 8 MA/m-class pulsed field magnetometer has been constructed by composing a pulsed field magnet, a pickup coil, analog integrators, a digital storage oscilloscope and a personal computer. For precision measurements, a 3-axis compensation principle has been applied for the fabrication of pickup coil, and the compensation level of the order of $10^{-6}$ and the sensitivity of $5{\cdot}10^{-7}\;Am^2$ for magnetic moment have been obtained. The high sensitivity of the magnetometer is good enough for measurements of magnetic properties of rare earth magnets in small size or thin films shorter than $3\;mm{\phi}$ in diameter.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.507-508
• /
• 2006

High performance delta-sigma modulator is developed for audio-codec applications(i.e.. 16-bit resolution at a 20kHz signal bandwidth). The modulator is realized with fully-differential switched capacitor integrators. All stages employ a single-stage folded-cascode amplifier. The presented delta-sigma modulator when clocked at 3.2MHz achieves 85.2dB peak-SNDR and 94.8dB SNR. This modulator is designed in a SAMSUNG $0.18{\mu}m$ CMOS process. Finally, this paper shows the test setup and FFT result gained from delta-sigma modulator chip designed for audio applications.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.4
• /
• pp.28-34
• /
• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.7
• /
• pp.39-46
• /
• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.