• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.39-45
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• 2009

In this paper, we discuss hardware design and deployment issues in current passive UHF RFID systems. Using the link budget concept, the methodology to calculate forward- and reverse-link interrogation range is shown. Then, we consider hardware issues: phase diversity, phase noise with range correlation, and TX leakage problems. Finally, three interference problems when deploying RFID systems are presented.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.100-107
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• 1994

This article describes the hardware design scheme of Hamming MAXNET algorithm which is appropriate for binary pattern classification with minimum HD measurement between stimulus vector and storage vector. Circuit integration is profitable to Hamming MAXNET because the structure of hamming network have a few connection nodes over the similar neuro-algorithms. Designed hardware is the two-layered structure composed of hamming network and MAXNET which enable the characteristics of low power consumption and fast operation with biline volgate sensing scheme. Proposed Hamming MAXNET hardware was designed as quantize-level converter for simulation, resulting in the expected binary pattern convergence property.

• Journal of Korean Association for Spatial Structures
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• v.16 no.4
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• pp.75-82
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• 2016

Building hardware joints are welded in most cases, which have risks of fire and explosion. Besides, the secondary damage of the destruction of the welded parts can be caused by the horizontal displacement of the structure due to earthquake or wind load. This paper compared the horizontal displacement following abilities of welded building hardware and non-welded building hardware. To do this, We conducted actual formation shake table test, and checked on the horizontal displacement following ability of structure by comparing their responses to earthquake load. We made the 2m-high framework to examine the responses of the actually constructed building hardwares, and analyzed the displacement responses of the welded-typed, non-welded-typed, and cruciform bracket building hardwares. We conducted the test by increasing acceleration rate until displacement reached 40mm corresponding to allowable relative story displacement II. The result of the test showed that the building hardware using welding work made cracking and breakage on welded connections of welded building hardware, but non-welded building hardware with no use of welding work and cruciform bracket building hardware make no problem, and that non-welded building hardware is superior to that of the welded building hardware in the horizontal displacement following ability due to earthquake or wind load.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1187-1188
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• 2008

An area of research called evolvable hardware has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. In this paper, we have studied and surveyed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm(GA) hardware, reconfigurable hardware logic, and the control logic. In this paper, we describe the architecture, functions of the chip.

• Proceedings of the Korean Reliability Society Conference
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• 2011.06a
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• pp.271-279
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• 2011

Automotive safety integrity level of hardware components can be achieved by satisfying quantitative and qualitative requirements. Based on ASIL, quantitative requirements are composed of hardware architectural metrics and evaluation of safety goal violations due to random hardware failures in ISO 26262. In this paper, the types of hardware failures will be defined and classified. Based on various metrics related with hardware failures, design essentials to achieve hardware safety integrity will be studied specifically. Issues associated with hardware development and assessment process are presented briefly.

• Journal of Korea Multimedia Society
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• v.19 no.4
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• pp.747-755
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• 2016

Automated guided vehicles have been used for a long time to increase work efficiency in the logistics field, but it is difficult to apply to a variety of logistics sites due to either the restricted movement mechanism or expensive devices. In this paper, we present a flexible software architecture that is hardware-independent for a mobile power cart of the follow mode and implement it using a ROS software platform. Through the SCV analysis for the system functionalities, we design a package to track a user movement and a package to control a new hardware platform. It has an advantage to use a variety of movement algorithms and hardware platforms by applying the strategy pattern and the template method pattern for the design of a software architecture. Through the performance evaluation, we show that the proposed design is maintainable in terms of a software complexity and it detects a user's movement by obtaining a user skeleton information so that it can control a hardware platform to move at a certain distance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.269-277
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• 1986

This paper proposes a new algorithmic state machine(ASM) chart and a new hardware description for automatic logic design of VLSI. To describe the behavioral characteristics of the design specification, the conventional ASM chart is modified, and a new hardware description language, SDL, is proposed. The SDL is one-to-one correspondent to the proposed ASM chart symbol, and can be used in a hierachical design of VLSI. As a design example, we obtain a logic circuit diagram of gate lebel utilizing a SDL hardware compiler after drawing an ASM chart and describing in SDL.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.231-239
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• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

• Archives of design research
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• v.17 no.4
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• pp.119-128
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• 2004

There is a lack of user centered design methods that support effective collaboration between designers and end-users for designing hardware and software integrated digital products. This paper presents the application of Collaborative Design and a new collaborative design prototyping tool for interactive digital product design projects. The tool consists of STCtools(State Transition Chart tools) software, hardware modeling materials, and physical interface toolkits for integrating software and hardware. STCtools allow users to create and edit States, to compose Events describing transitions between States, and to run intermediate or final results of STC. Using the hardware modeling materials and the physical interface toolkit, designers and end-users can collaborately examine the hardware and software integrated concepts in an early stage of the design process. Three collaborative design workshops of designing a portable digital guide for a theme park were accomplished to examine the feasibility of the tool. The results suggested that the tool supported iterative concept development and interactions between designers and end users. Although several user interface problems of STCtools were identified, the participants gave positive feedback on the role of the tool in collaborative concept generation and deployment. It is expected that the results of this study contribute not only to the collaboration between designers and end users, but also to the collaboration between designers, and between designers and other professionals.