Browse > Article

A Hardware Design Space Exploration toward Low-Area and High-Performance Architecture for the 128-bit Block Cipher Algorithm SEED  

Yi, Kang (한동대학교 전산전자공학부)
Publication Information
Journal of KIISE:Computing Practices and Letters / v.13, no.4, 2007 , pp. 231-239 More about this Journal
Abstract
This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.
Keywords
SEED; 128-bit symmetric block cipher algorithm; FPGA; hardware design space exploration; area-performance trade-offs; cryptography processor;
Citations & Related Records
연도 인용수 순위
  • Reference
1 이강, 박예철, '내장형 시스템을 위한 128비트 블록 암호화 알고리즘의 저비용 FPGA를 이용한 설계 및 구현', 한국정보과학회 논문지 : 시스템 및 이론(Journal of KISS : Computer Systems and Theory), Vol.31, No.7.8, pp. 402-413, 2004년, 8월
2 전신우, 정용진, '128비트 SEED 암호화 알고리즘의 고속처리를 위한 하드웨어 구현', 통신정보보호학회논문집, 제11권, 제1호, 2001년, 2월
3 Miron Abramovici, Jose T. de Sousa,Daniel Saab, 'A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware,' Proceedings of the 36th ACM/IEEE conference on Design automation conference June 1999
4 Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen, '(When) Will FPGAs Kill ASICs,' Proceedings of the 38th conference on Design automation June 2001, pp. 321-322
5 채수봉, 김기용, 조용범, 'Pipeline 구조의 SEED 암호화 프로세서 구현 및 설계', 대한전자공학회 02 하계종합학술대회 논문집(2), 2002.06 pp. 125-128
6 Young-Ho Seo, Jong-Hyeon Kim, Yong-Jin Jung, and Dong-Wook Kim, 'An Area Efficient Implementation of 128-bit Block Cipher, SEED,' ITC-CSCC 2000, Korea, 2000
7 한국정보보호진흥원(KISA), '128비트 블록 암호알고리즘 표준',
8 엄성용, 이규원, 박선화, 'SEED 블록 암호 알고리즘의 파이프라인 하드웨어 설계', 정보과학회 논문지, 시스템 및 이론 제30권 제3호, pp. 149-159, 2003년 4월
9 정진욱, 최병윤, 'SEED와 TDES 암호 알고리즘을 구현하는 암호 프로세서의 VLSI 설계', 대한전자공학회 하계 종합 학술대회 논문집, 제23권, 제1호, pp.166-172, 2000년, 6월
10 신종호, 강준우, 'SEED 블록 암호 알고리즘의 단일칩 연구', 대한전자공학회 하계종합학술대회 논문집, 제23권, 제1호, pp. 165-168, 2000년
11 김종현, 서영호, 김동욱 '블록 암호 알고리즘 SEED의 면적 효율성을 고려한 FPGA 구현', 정보과학회논문지, 컴퓨팅의 실제 제7권, 제4호, pp. 372-381, 2001년 8월