• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.305-308
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• 2001

This paper describes the design of elliptic curve cryptographic (ECC) coprocessor over binary fields for the If card. This coprocessor is implemented by the shift-and-add algorithm for the field multiplication algorithm. And the modified almost inverse algorithm(MAIA) is selected for the inverse multiplication algorithm. These two algorithms is merged to minimize the hardware size. Scalar multiplication is performed by the binary Non Adjacent Format(NAF) method. The ECC we have implemented is defined over the field GF(2$^{163}$), which is a SEC-2 recommendation［7］..

• ETRI Journal
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• v.30 no.3
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• pp.365-376
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• 2008

This paper presents the design and implementation of a hyperelliptic curve cryptography (HECC) coprocessor over affine and projective coordinates, along with measurements of its performance, hardware complexity, and power consumption. We applied several design techniques, including parallelism, pipelining, and loop unrolling, in designing field arithmetic units, group operation units, and scalar multiplication units to improve the performance and power consumption. Our affine and projective coordinate-based HECC processors execute in 0.436 ms and 0.531 ms, respectively, based on the underlying field GF($2^{89}$). These results are about five times faster than those for previous hardware implementations and at least 13 times better in terms of area-time products. Further results suggest that neither case is superior to the other when considering the hardware complexity and performance. The characteristics of our proposed HECC coprocessor show that it is applicable to high-speed network applications as well as resource-constrained environments, such as PDAs, smart cards, and so on.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2748-2750
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• 1999

This Paper describes the design of an induction motor control using the TMS320C32 Digital Signal Processor and the ADMC201 motion coprocessor. Presented hardware architecture can be used for several industry applications with wide range of speed control, e.g. elevator and cranes application, servo motor, electrical vehicles. The main purpose of the paper is demonstration of the implementation and maximum utilization of the ADMC201 motion coprocessor in digital vector control system for AC drives.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.119-127
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• 1998

In this paper, the design of a VLSI-based multilayer neural network is presented, which can be used as a dedicated hardware for character-type segmentation and character-element recogniti on consuming large processing time in conventional software-based Hangul printed-character recognition systems. Also the architecture and its design of a neural coprocessor interfacing the neural network with a host computcr and controlling thc neural network are presented. The architecture, behavior, and performance of the proposed neural coprocessor are justified using VHDL modeling and simulation. Experimental results show the successful rates of character-type segmentation and character-element recognition is competitive to those of software-based Hangul printed-character recognition systems with retaining high-speed.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.492-495
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• 1999

In this paper, a research is focused on implementation of the handwritten Korean-character recognition system using a neural coprocessor for PDA application. The proposed coprocessor is composed of a digital neural network called DMNN and a RISC-based dedicated controller in order to achieve high speed as well as compactness. Two neural networks are used for recognition, one for stroke classification out of extended 11 strokes and the other for grapheme classification. Our experimental result shows that the successful recognition rate of 92.1% over 3,000 characters written by 10 persons can be obtained. Moreover, it can be improved to 95.3% when four candidates are considered. The design verification of tile proposed neural coprocessor is conducted using the ASIC emulator for further hardware implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.4
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• pp.508-514
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• 2020

To implement the continuously evolving mobile communication standards such as Long Term Evolution (LTE) and 5G, the Software Defined Radio (SDR) concept provides great flexibility and efficiency. For many years, a high-end Digital Signal Processor (DSP) System on Chip (SoC) has been developed to support multicore and various hardware coprocessors. This paper introduces the implementation of the SDR platform hardware using TI's TCI663x chip. Using the platform, LTE transport channel is implemented by interworking multicore DSP with Bit rate Coprocessor (BCP) and Turbo Decoder Coprocessor (TCP) and the performance is evaluated according to various implementation options. In order to evaluate the performance of the implemented LTE transport channel, LTE base station system was constructed by combining FPGA main board for physical channels, SDR platform board, and RF & Antenna board.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2189-2196
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• 2014

In this paper, a VLIW(Very Long Instruction Word) vision coprocessor which can efficiently accelerate computer vision algorithm for automotive is designed. The VLIW coprocessor executes four instructions per clock cycle via 8-stage pipelined structure and has 36 integer and floating-point instructions to accelerate computer vision algorithm for pedestrian detection. The processor has about 300-MHz operating frequency and about 210,900 gates under 45nm CMOS technology and its estimated performance is 1.2 GOPS(Giga Operations Per Second). The vision system composed of vision primitive engine and eight VLIW coprocessors can execute pedestrian detection at 25~29 frames per second(FPS). Because the VLIW coprocessor has high detection rate and loosely coupled interface with host processor, it can be efficiently applicable to a wide range of vision applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.63-72
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• 2007

In this paper, we propose a novel reconfigurable coprocessor for multimedia mobile terminals. Because most of multimedia operations require fast operations of large amount of data in the limited clock frequency, it is necessary to enhance the performance of the embedded processor that is widely used in current multimedia mobile terminals. Therefore, we proposed and have designed the coprocessor which had the ability of fast operations of multimedia data. The proposed coprocessor was not only reconfigurable, but also flexible and expandable. The proposed coprocessor has been designed by using VHDL and compared with previous reconfigurable coprocessors and a commercial embedded processor in architecture and speed. As a result of the architectural comparison, the proposed coprocessor had better structure in terms of hardware size and flexibility. Also, the simulation results of DCT application showed that the proposed coprocessor was 26 times faster than a commercial ARM processor and 11 times faster than the ARM processor with fast DCT core.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1058-1067
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• 2004

Java virtual machine provides code compactness, simple execution engines, and platform-independence which are important features for small devices such as mobile or embedded device, but it has a big problem, such as low throughput due to stack-oriented operation. In this paper hardware lava accelerator targeted for mobile or embedded application is designed to eliminate the slow speed problem of lava virtual machine. The designed lava accelerator can execute 81 instructions of Java virtual machine(JVM)'s opcodes and be used as Java coprocessor of conventional 32-bit RISC processor with efficient coprocessor interface and instruction buffer. It consists of about 14,300 gates and its maximum operating frequency is about 50 Mhz under 0.35um CMOS technology.