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http://dx.doi.org/10.6109/jkiice.2014.18.9.2189

Hardware Design of VLIW coprocessor for Computer Vision Application  

Choi, Byeong-Yoon (Department of Computer Engineering, Dongeui University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.18, no.9, 2014 , pp. 2189-2196 More about this Journal
Abstract
In this paper, a VLIW(Very Long Instruction Word) vision coprocessor which can efficiently accelerate computer vision algorithm for automotive is designed. The VLIW coprocessor executes four instructions per clock cycle via 8-stage pipelined structure and has 36 integer and floating-point instructions to accelerate computer vision algorithm for pedestrian detection. The processor has about 300-MHz operating frequency and about 210,900 gates under 45nm CMOS technology and its estimated performance is 1.2 GOPS(Giga Operations Per Second). The vision system composed of vision primitive engine and eight VLIW coprocessors can execute pedestrian detection at 25~29 frames per second(FPS). Because the VLIW coprocessor has high detection rate and loosely coupled interface with host processor, it can be efficiently applicable to a wide range of vision applications.
Keywords
vliw; computer vision; SoC; ADAS(Automatic Driving Assistance System);
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