• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.7
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• pp.956-962
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• 2020

Recently, as the size of data used in an embedded system increases, the need for an ECC decoding operation to robustly receive a massive data is emphasized. In this paper, we propose a method to accelerate the execution of computations that derive syndrome vectors when ECC decoding is performed using Hamming code in an embedded system with a built-in GPU. The proposed acceleration method uses the matrix-vector multiplication of the decoding operation using the CSR format, one of the data structures representing sparse matrix, and is performed in parallel in the CUDA kernel of the GPU. We evaluated the proposed method using a target embedded board with a GPU, and the result shows that the execution time is reduced when ECC decoding operation accelerated based on the GPU than used only CPU.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.8
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• pp.491-494
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• 2000

A scheme is proposed for measuring similarities between the binary pulse signals in the pulse-code modulation using the Integra-Normalizer. The Integra-Normalizer provides a better interpretation of the relationship between the pulse signals by removing redundant codes, which maps all possible observed signals to one of the codes to be received with relative similarities between each pair of compared signals. The proposed method provides better error tolerance than L2 metric, such as Hamming distance, since the distances between pulse signals are measured not useful for the time-delay detection in the pulse-code modulation.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.109-114
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• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• Journal of Intelligence and Information Systems
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• v.13 no.4
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• pp.65-78
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• 2007

This paper proposes a new method of weighted template matching for machine-printed numeral recognition. The proposed weighted template matching, which emphasizes the feature of a pattern using adaptive Hamming distance on local feature areas, improves the recognition rate while template matching processes an input image as one global feature. Template matching is vulnerable to random noises that generate ragged outlines of a pattern when it is binarized. This paper offers a method of chain code trimming in order to remove ragged outlines. The method corrects specific chain codes within the chain codes of the inner and the outer contour of a pattern. The experiment compares confusion matrices of both the template matching and the proposed weighted template matching with chain code trimming. The result shows that the proposed method improves fairly the recognition rate of the machine-printed numerals.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.50-56
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• 2003

This paper proposes a coding scheme of control channel for mobile packet communication to maximize the minimum Hamming distance, which is based on shifting of basis vectors of Reed Muller code with optimized dynamic puncturing and/or(partial) sequence repetition. Since the maximum likelihood decoding can be performed using the extremely simple FHT(Fast Hadamard Transformation), it is suitable for real time optimum decoding of control channel information with very little complexity. We show applications of the proposed coding method to TFCI(Transport Format Combination Indicator) code in split and normal modes of 3GPP W-CDMA system. We also discuss how this method can reduce rate indication error over AWGN(Additive White Gaussian Noise) as well as fading channels when the proposed coding scheme is applied to 1xEV-DV system of $3^{rd}$TEX> generation partnership project 2(3GPP2) to indicate the data rate transmitted on the reverse traffic channel by a Mobile Station(MS).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.8
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• pp.1128-1135
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• 1993

In this paper, new binary cyclic codes (hereafter, refered to as GMW code) which are generated by using GMW sequence, g(t) = tr((trk(a))r), and its cyclic shifts are introduced. Code length of GMW codes is 2a-1, where k is composite integer, e·J. Dimension of the GMW codes is k(k/j)w-1, where w is a Hamming weight of r. Several properties of GMW codes such as designed distance, minimum distance, and weights of code words are obtained in terms of parameters of GMW sequences. And expansion of GMW sequences in terms of m-sequence and its decimation sequences are introduced and characteristic polynomials of GMW sequences are also derived.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.43-50
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• 1990

Using the trace mapping, we suggest the generating algorithm of non-binary GMW code sequences, to expand the ground field GF(2) into GF(p), p>2. And constructing non-binary GMW code sequences over GF(3) and GF(5), respectively, it is shown that they have the Hamming autocorrelation functions identical to m-sequences, non-linearity to improve the disadvantages of linearity, and balance properties.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.586-589
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• 2013

In this paper, the proposed scheme is STBC system combined with convolutional code to ensure the reliability of data transmission for a high rate wireless communication. In addition, this scheme uses a modified viterbi algorithm in order to get a high system gain when data is transmitted. Because we combine STBC and comvolutional code, the proposed scheme can get a diversity gain of STBC and coding gain of convolutional code at the same time. Unlike existing viterbi docoding algorithm using Hamming distance in order to calculate branch matrix, the modified viterbi algorithm uses Euclidean distance value between received symbol and reference symbol. To analyze the system proposed, it was simulated by changing the constraint length of the convolutional code and the number of transmit and receive antennas of STBC.