Browse > Article
http://dx.doi.org/10.6109/jkiice.2020.24.7.956

Acceleration of ECC Computation for Robust Massive Data Reception under GPU-based Embedded Systems  

Kwon, Jisu (School of Electronic Engineering, Kyungpook National University)
Park, Daejin (School of Electronic Engineering, Kyungpook National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.24, no.7, 2020 , pp. 956-962 More about this Journal
Abstract
Recently, as the size of data used in an embedded system increases, the need for an ECC decoding operation to robustly receive a massive data is emphasized. In this paper, we propose a method to accelerate the execution of computations that derive syndrome vectors when ECC decoding is performed using Hamming code in an embedded system with a built-in GPU. The proposed acceleration method uses the matrix-vector multiplication of the decoding operation using the CSR format, one of the data structures representing sparse matrix, and is performed in parallel in the CUDA kernel of the GPU. We evaluated the proposed method using a target embedded board with a GPU, and the result shows that the execution time is reduced when ECC decoding operation accelerated based on the GPU than used only CPU.
Keywords
Error correction code; GPU acceleration; Hamming code; Sparse matrix-vector multiplication;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 V. S. Chua, J. Z. Esquivel, A. S. Paul, T. Techathamnukool, C. F. Fajardo, N. Jain, O. Tickoo, R. Iyer, "Visual IoT: Ultra-Low-Power Processing Architectures and Implications," IEEE Micro, vol. 37, no. 6, pp. 52-61, November/December 2017.   DOI
2 D. H. Hwang and K. S. Jang, "Fast Hand-Gesture Recognition Algorithm For Embedded System," Journal of the Korea Institute of Information and Communication Engineering, vol. 21, no. 7, pp. 1349-1354, Jul. 2017.   DOI
3 S. Y. Cho, "Design and Implementation of Fail Recovery Process on Highly-Reliable Embedded Linux System," Journal of Security Engineering, vol.11, no.2, pp. 89-100, Feb. 2014.   DOI
4 R. Motwani, Z. Kwok, S. Nelson, "Low density parity check (LDPC) codes and the need for stronger ECC," Flash Memory Summit, 2011.
5 K. Sripimanwat, Turbo Code Applications, Vol. 1. Dordrecht: Springer, 2005.
6 W. Liu, J. Rho, W. Sung, "Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories," in 2006 IEEE Workshop on Signal Processing Systems Design and Implementation. pp. 303-308, 2006.
7 S. Keskin and T. Kocak, "GPU accelerated gigabit level BCH and LDPC concatenated coding system," in 2017 IEEE High Performance Extreme Computing Conference (HPEC), Waltham: MA, pp. 1-4, 2017.
8 A. K. Subbiah and T. Ogunfunmi, "Memory-efficient Error Correction Scheme for Flash Memories using GPU," in 2018 IEEE International Workshop on Signal Processing Systems (SiPS), Cape Town, pp. 118-122, 2018.
9 S. Kim, J. Cho and D. Park, "Moving-Target Position Estimation Using GPU-Based Particle Filter for IoT Sensing Applications," Applied Sciences, vol. 7, no. 11, pp. 1152, Nov. 2017.   DOI
10 S. Kim, J. Cho and D. Park, "Accelerated DEVS Simulation Using Collaborative Computation on Multi-Cores and GPUs for Fire-Spreading IoT Sensing Applications," Applied Sciences, vol. 8, no. 9, pp. 1466, Aug. 2018.   DOI
11 A. K. Subbiah and T. Ogunfunmi, "Three-bit fast error corrector for BCH codes on GPUs," in 2019 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas: NV, pp. 1-4, 2019.
12 H. L. Kalter, C. H. Stapper, J. E. Barth, J. DiLorenzo, C. E. Drake, J. A. Fifield, G. A. Kelly, S. C. Lewis, W. B. van der Hoeven, J. A. Yankosky, "A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC," IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1118-1128, Oct. 1990.   DOI
13 T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato, Y. Takeuchi, K. Ohuchi, "A compact on-chip ECC for low cost flash memories," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 662-669, May 1997.   DOI
14 K. Dang and X. Tran, "Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication," in 2018 IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, pp. 154-161, 2018.