• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.443-450
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• 2013

This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.

• Journal of IKEEE
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• v.15 no.3
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• pp.205-210
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• 2011

A novel hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. The threshold voltage of the suggested comparator circuit is controlled by 234mV by change of 4 digital control bits in the simulation, which is a close agreement to the analytic calculation.

• The Bulletin of The Korean Astronomical Society
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• v.43 no.1
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• pp.55.1-55.1
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• 2018

Studies on rotation-powered pulsars with strong surface magnetic field may help us clarify the unclear link between magnetars and canonical radio pulsars because the magnetar-like emission is expected to be observed. PSR J1119-6127 associated with SNR G292.2-0.5 has a high magnetic field of $4.1{\times}1013$ gauss, and a young characteristic age of ~1700 years can be served as the good candidate to compare with magnetars and rotation-powered pulsars. The glitch accompanied by the radiative changes detected in 2007 is the first case we observed for a rotationally powered radio pulsar. This pulsar experienced magnetar-like outbursts in mid. 2016, similar to the 2006 transition occurred on the other radio-quiet rotation-powered pulsar with strong surface magnetic field, PSR J1846-0258. In this talk, I'll report the investigation with X-ray and gamma-ray data of this magnetar-like pulsar. A sudden decrease in the gamma-ray emission at the GeV band was detected immediately after the X-ray outburst. Accompanying with the disappearance of the radio pulsation, the gamma-ray pulsation cannot be resolved as well after the outburst. We tried to derive the timing behavior and some intriguing features of this pulsar in this work corresponding to the outburst using the Swift data, NuSTAR and XMM observations.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1582-1589
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• 2000

A dynamic D-flipflop is proposed aiming at low power and high frequency(GHz) operations. The proposed D-flipflop uses a smaller number of pmos transistors that it operates high speed in same dimensions. Also, it consumes lower power than conventional approaches by a shared nmos with clock input. In order to compare the performance of the proposed D-flipflop, we perform simulation estimating power consumption and maximum operating frequency of each same dimension D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop. A high speed dual-modulus prescaler employing the proposed D-flipflop is evaluated via the same method. The simulation results show that the proposed D-fliplflop has good performance than conventional circuits.

• Journal of IKEEE
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• v.23 no.3
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• pp.1046-1053
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• 2019

In a multi-channel single-ended system, the far-end crosstalk (FEXT) due to mutual inductance and mutual capacitance between two adjacent channels critically limit the bandwidth. FEXT causes crosstalk-induced jitter (CIJ) and crosstalk-induced glitch (CIG) which leads to timing margin and voltage margin degradations, respectively. Therefore, FEXT must be compensated in order to increase eye opening and achieve high data-rate. It can be compensated in transmitter by controlling the timing of the data or reshaping the waveform of the signal. Also, FEXT can be compensated in receiver by generating mimicked FEXT using high-pass filter. In this paper, recent techniques to compensate FEXT are investigated, with discussions of their pros and cons.

• The Bulletin of The Korean Astronomical Society
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• v.46 no.2
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• pp.74.2-75
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• 2021

We demonstrate that a deep learning classifier that only uses to gravitational wave (GW) detectors auxiliary channel data can distinguish various types of non-Gaussian noise transients (glitches) with significant accuracy, i.e., ≳ 80%. The classifier is implemented using the multi-scale neural networks (MSNN) with PyTorch. The glitches appearing in the GW strain data have been one of the main obstacles that degrade the sensitivity of the gravitational detectors, consequently hindering the detection and parameterization of the GW signals. Numerous efforts have been devoted to tracking down their origins and to mitigating them. However, there remain many glitches of which origins are not unveiled. We apply the MSNN classifier to the auxiliary channel data corresponding to publicly available GravitySpy glitch samples of LIGO O1 run without using GW strain data. Investigation of the auxiliary channel data of the segments that coincide to the glitches in the GW strain channel is particularly useful for finding the noise sources, because they record physical and environmental conditions and the status of each part of the detector. By only using the auxiliary channel data, this classifier can provide us with the independent view on the data quality and potentially gives us hints to the origins of the glitches, when using the explainable AI technique such as Layer-wise Relevance Propagation or GradCAM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.35-42
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• 2010

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1281-1286
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• 2008

The PSK carrier signal recovery circuit using a six-port phase correlator was analyzed and the circuit structure is proposed in this paper. The proposed carrier signal recovery circuit that is made of reflection element and six-port phase correlator, which is comprised of a power divider and three hybrid branch line couplers, give a simple structure and can be fabricated without no difficulty. The circuit recovers the carrier signal of BPSK and QPSK modulation signal. The proposed scheme can be utilized as a basis structure for high-mode PSK carrier signal recovery. By simulation results, the recovered signal by the proposed circuit shows a good carrier signal characteristic with CW signal of a constant phase($23.4^{\circ}$) and ${\pm}0.8^{\circ}$ phase error due to glitch conditions.