• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1055-1061
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• 2002

Conventional TSPC D flip-flop has the advantages of high speed, simple clock distribution, and no racing because of the single phase clocking strategy and its simple structure. But, it suffers from glitch, clock slope sensitivity and unbalanced propagation delay problems. Therefore, a new dynamic D flip-flop, which improves these disadvantages, is proposed. The main idea of this paper is DS(Discharge Suppression) scheme, which suppresses unnecessary discharge. As a result, the proposed structure is free from glitch problem and it improves maximum clock slope immunity from 0.25ns to Ins. Also, it uses only 8 transistors and it Is demonstrated that high speed operation is feasible by balancing propagation delay time.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• The Bulletin of The Korean Astronomical Society
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• v.40 no.2
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• pp.55.3-55.3
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• 2015

We study the possibility of new approach for identifying instrumental noise artifacts and sources of gravitational wave (GW) data such as LIGO and CLIO using various correlation analyses.To improve the quality of data for the GW signal search, the instrumental noises should be reduced in an appropriate way. Furthermore, it is important to understand the correlation between auxiliary channels of the GW detector. In this study, we investigate the possible way of identifying glitch triggers by generating time-frequency-correlation (TFC) maps between the related channels and compare the result to the current conventional schemes.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.01a
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• pp.145-146
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• 2017

본 논문에서는 CPLD 구조를 고려한 게이트 레벨 글리치 제거 방법에 대해 제안하였다. CPLD는 AND-OR 게이트의 2단 구조를 가진 LE를 기본 구조로 구성되어 있는 소자이다. CPLD로 구현할 회로에 대한 DAG를 CPLD 구조에 맞도록 그래프를 분할하여 매핑가능클러스터를 생성한다. 생성된 매핑가능클러스터는 내부의 글리치와 전체 회로에 대한 글리치 발생 가능성을 검사하여 글리치를 제거한다. AND게이트와 OR게이트를 사용하는 2단 구조는 게이트가 달라 글리치가 발생될 수 있는 가능성을 검사하기 어렵다는 단점이 있어 AND-OR 게이트의 2단 구조와 동일한 구조를 가지고 있으며 게이트가 동일한 NAND 게이트를 이용하여 전체 회로를 변환한 후 글리치 발생여부를 검사함으로서 정확한 글리치 발생 가능성을 제거한다. 실험 결과는 제안 된 알고리즘 [10]과 비교하였다. 소비 전력이 2 % 감소되어 본논문에서 제안한 방법의 효율성이 입증되었다.

• The Bulletin of The Korean Astronomical Society
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• v.36 no.1
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• pp.47.2-47.2
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• 2011

Gravitational waves from the pulsar glitch can be detected by next generation gravitational wave observatories. We investigate characteristics of the modes that can emit the gravitational waves excited by three different types of perturbations satisfying conservation of total rest mass and angular momentum. These perturbations mimic the pulsar glitch theories i.e., change of moment of inertia due to the star quakes or angular momentum transfer by vortex unpinning at crust-core interface. We carry out numerical hydrodynamic simulations using the pseudo-Newtonian method which makes weak field approximation for the dynamics, but taking all forms of energies into account to compute the Newtonian potential. Unlike other works, we found that the first and second strongest modes that give gravitational waves are $^2p_1$ and $H_1$ rather than$^2f$. We also found that vortex unpinning model excites the inertial mode in quadrupole moment quite effectively. The inertial mode may evolve into the non-axisymmetric r-mode.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.8
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• pp.406-413
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• 2001

본 논문은 CMOS 디지털 회로에서 글리치(glitch)에 의해 발생하는 전력소모를 줄이기 위한 효율적인 휴리스틱 알고리즘을 제시한다. 제안된 알고리즘은 사이징되는 게이트의 위치와 양에 따라 게이트 사이징을 세 가지 type으로 분류한다. 또한 버퍼삽입은 삽입되는 버퍼의 위치에 따라서 두 가지 type으로 분류한다. 글리치 제거 효과를 극대화하기 위해서 비용과 이득의 상관관계를 고려하여 하나의 최적화 과정 안에서 세 가지 type의 게이트 사이징과 두 가지 type의 버퍼삽입을 혼합한다. 제안된 알고리즘은 0.5$\mu\textrm{m}$ 표준 셀 라이브러리(standard cell library)를 이용한 LGSynth91 벤치마크 회로에 대한 테스트 결과 효율성을 검증하였다. 실험결과는 평균적으로 69.98%의 글리치 감소와 28.69%의 전력감소를 얻을 수 있었으며 이것은 독립적으로 적용된 게이트 사이징과 버퍼 삽입 알고리즘에 의한 것 보다 좋은 결과이다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.83-90
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• 2007

In this paper, we propose an implementation and an algorithm of 'Jitter and Glitch Removing Circuit' for UHF RFID reader system based on ISO/IEC 18000-6C standard. We analyze the response of TI(Texas Instrument) Gen2 tag with a reader using the proposed algorithm. In ISO/IEC 18000-6C standard, a bit rate accuracy(tolerance) is up to +/-22% during tag-to-interrogator communication and +/-1% during interrogator-to-tag communication. In order to solve tolerance problems, we implement the Jitter and Glitch Removing Circuit using the concept of tolerance and tolerance-accumulation instead of PLL(DPLL, ADPLL). The main clock is 19.2MHz and the LF(Link Frequency) is determined as 40kHz to meet the local radio regulation in korea. As a result of simulations, the error-rate is zero within 15% tolerance of tag responses. And in the case of using the adaptive LF generation circuit, the error-rate varies from 0.000589 to zero between 15% and 22% tolerance of tag responses. In conclusion, the error-rate is zero between 0%-22% tolerance of tag response specified in ISO/IEC 18000-6C standard.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.221-227
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• 2014

When implementing cryptographic algorithms in mobile devices like smart cards, the security against side-channel attacks should be considered. Side-channel attacks try to find critical information from the side-channel infromation obtained from the underlying cryptographic devices' execution. Especially, the power analysis attack uses the power consumption profile of the devices as the side-channel information. This paper proposes a new gate-level countermeasure against the power analysis attack and the glitch attack and suggests how to apply the measure to securely implement AES.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.52-57
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• 1999

It is very important to design of QAM modulator of high spectral efficiency for high speed data transmission. In this paper, typical 16-QAM modulator is designed by modification design of DDFS(direct digital frequency synthesizer). DDFS generates sinusoidal waveform digitally to the frequency setting word. Phase modulation is accuratly made by control of a generated phase increment value and amplitude modulation is accomplished in the D/A converter output by control of amplitude level. For the suppression of harmonics and glitch, dual-structured DDFS is studied to improve the spurious characteristics. P-Spice is used for design and simulation in mixed mode. Also we can get the satisfactory results of designed 16-QAM modulator from the constellation output.