• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.577-580
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• 2004

Our paper focus on crosstalk noise problem, especially crosstalk glitch that occurs when victim is stable state and aggressor is transitive state. This generated glitch weigh with the functional reliability if the glitch is considerable. In this paper, we use buffer insertion, down sizing, buffer insertion with up-sizing methods concurrently. These methodologies use filtering effects which gates that have bigger noise margin than glitch width eliminates glitch. In addition, we do limited optimization in boundary of node's slack. Therefore, the operated node's changes are for nothing in other node's slack.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1058-1061
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• 2002

This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.35-43
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• 2006

In the paper, we propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in Statistical Static Timing Analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of proposed method has been verified on ISCAS85 benchmark circuits with $0.16{\mu}m$ model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.61-64
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• 2003

In this paper, we implement PAMD(Positive Answering Machine Detection) for discrimination human and ARS. We are used Grunt detection, Glitch Noise detection and Tone detection for PAMD. It distinguishes voice signals from ring-back tone and glitch noise respectively. And as a second step, it judges whether human responses or ARS responses after integrating pattern changes like initial response period, the number of voice data, each time of voice data period and glitch noise. The accuracy is about 9375 in ASR and about 98％ in Mobile phone.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.455-458
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• 2004

We present an efficient heuristic algorithm to reduce glitch power dissipation in combinational circuits. In this paper, the total number of glitches are reduced by replacing existing gates with functionally equivalent ones and by gate sizing which classified into three types and by buffer insertion which classified into two types. The proposed algorithm combines gate freezing, gate sizing. and buffer insertion into a single optimization process to maximize the glitch reduction. Our experimental results show an average of $67.8\%$ glitch reduction and $32.0\%$ power reduction by simultaneous gate freezing, gate sizing, and buffer insertion.

• Journal of Digital Contents Society
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• v.13 no.1
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• pp.37-41
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• 2012

In this paper, we proposed FPGA algorithm for consider the power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within FPGA. Separated the feasible cluster reduced power consumption using glitch removal method. Glitch removal appled delay buffer insertion method by signal process within the feasible cluster. Also, removal glitch between the feasible clusters by signal process for circuit. The experiments results show reduction in the power consumption by 7.14% comparing with that of [9].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.2
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.5
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• pp.195-200
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• 2009

CRT-based RSA algorithm, which was implemented on smartcard, microcontroller and so on, leakages secret primes p and q by fault attacks using laser injection, EM radiation, ion beam injection, voltage glitch injection and so on. Among the many fault injection methods, voltage glitch can be injected to target device without any modification, so more practical. In this paper, we made an experiment on the fault injection attack using abnormal source voltage. As a result, CRT-RSA's secret prime p and q are disclosed by fault attack with voltage glitch injection which was introduced by several previous papers, and also succeed the fault attack with source voltage blocking for proper period.