• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1250-1252
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• 1993

Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.2
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• pp.103-110
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• 2001

Gate oxide scaling for sub-l00nm CMOS devices has been studied. Issues on the gate oxide scaling are reviewed, which are boron penetration, reliability, and direct tunneling leakage currents. Reliability of Sub-2.0nm oxides and the device performance degradation due to boron penetration are investigated. Especially, the effect of gate leakage currents on the transistor characteristics is studied. As a result, it is proposed that thinner oxides than previous expectations may be usable as scaling proceeds. Based on the gate oxide thickness optimization process we have established, high performance CMOS transistors of $L_{gate}=70nm$ and $T_{ox}=1.4nm$ were fabricated, which showed excellent current drives of $860\mu\textrm{A}/\mu\textrm{m}$ (NMOS) and $350\mu\textrm{A}/\mu\textrm{m}$ (PMOS) at $I_{off}=10\mu\textrm{A}/\mu\textrm{m}$ and $V_dd=1.2V$, and CV/I of 1.60ps (NMOS) and 3.32ps(PMOS).

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.617-621
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• 2013

This study examined the effect of electron-beam (E-beam) irradiation on the electrical properties of n-GaN, AlGaN and AlGN/GaN structures on sapphire substrates. E-beam irradiation resulted in a significant decrease in the gate leakage current of the n-GaN, AlGaN and HEMT structure from $4.0{\times}10^{-4}A$, $6.5{\times}10^{-5}A$, $2.7{\times}10^{-8}A$ to $7.7{\times}10^{-5}A$, $7.7{\times}10^{-6}A$, $4.7{\times}10^{-9}A$, respectively, at a drain voltage of -10V. Furthermore, we also investigated the effect of E-beam irradiation on the AlGaN surface in AlGaN/GaN heterostructure high electron mobility transistors(HEMTs). The results showed that the maximum drain current density of the AlGaN/GaN HEMTs with E-beam irradiation was greatly improved, when compared to that of the AlGaN/GaN HEMTs without E-beam irradiation. These results strongly suggest that E-beam irradiation is a promising method to reduce leakage current of AlGaN/GaN HEMTs on sapphire through the neutralization the trap.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.411-414
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• 1999

70 ${\AA}$-thick oxides nitridied at various conditions were reoxidized at pemperatures of 900$^{\circ}C$ in dry-O$_2$ ambients for 5～40 mininutes. The gate oxide interface porperties as well as the oxide substrate interface properties of MOS(Metal Oxide Semiconductor) capacitors with various nitridation conditions, reoxidation conditions and pure oxidation condition were investigated. We stuided I$\sub$g/-V$\sub$g/ characteristics, $\Delta$V$\sub$g/ shift under constant current stress from electrical characteristics point of view and breakdown voltage from leakage current point of view of MOS capacitors with SiO$_2$, NO, RNO dielectrics. Overall, our experimental results show that reoxidized nitrided oxides show inproved charge trapping porperites, I$\sub$g/-V$\sub$g/ characteristics and gate $\Delta$V$\sub$g/ shift. It has also been shown that reoxidized nitridied oxide's leakage currented voltage is better than pure oxide's or nitrided oxide's from leakage current(1${\mu}$A) point of view.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.595-600
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• 2016

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between $109{\AA}$, $190{\AA}$, $387{\AA}$, and $818{\AA}$ which have the gate area $10^{-3}cm^2$. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.801-802
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• 1992

Poly Si TFTs have been fabricated from low temperature annealed a-Si films. I-V and C-V characteristics in the off-state region were measured. Analytical model for the leakage current in the off-state was suggested. In the measurement, capacitance increased abruptly with Increasing gate and drain voltage. This phenomena is attributed to the leakage current.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.