• Title/Summary/Keyword: gate resistance

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A Study on the Temperature Variation Characteristics of Power VDMOSFET (전력 VDMOSFET의 온도변화 특성에 관한 연구)

  • Lee, Woo-Sun
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.35 no.7
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    • pp.278-284
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    • 1986
  • Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bias shows both positive and negative resistance characteristics depending on the gate threshold voltage and gate-to source bias votage. In this paper, the decision method of the gate crossover voltage by the temperature variation and a new method to determine the gate threshold voltage graphecally are presented.

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A study on Improvement of sub 0.1$\mu\textrm{m}$VLSI CMOS device Ultra Thin Gate Oxide Quality Using Novel STI Structure (STI를 이용한 서브 0.1$\mu\textrm{m}$VLSI CMOS 소자에서의 초박막게이트산화막의 박막개선에 관한 연구)

  • 엄금용;오환술
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.9
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    • pp.729-734
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    • 2000
  • Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

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The Process and Fabrication of 500 V Unified Trench Gate Power MOSFET (500 V급 Unified Trench Gate Power MOSFET 공정 및 제작에 관한 연구)

  • Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.26 no.10
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    • pp.720-725
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    • 2013
  • Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have analyzed trench process, field limit ring process for fabrication of unified trench gate power MOSFET. And we have analyzed electrical characteristics of fabricated unified trench gate power MOSFET. The optimal trench process was based on SF6. After we carried out SEM measurement, we obtained superior trench gate and field limit ring process. And we compared electrical characteristics of planar and trench gate unified power MOSFET after completing device fabrication. As a result, the both of them was obtained 500 V breakdown voltage. However trench gate unified power MOSFET was shown improved Vth and on state voltage drop characteristics than planar gate unified power MOSFET.

Analysis of The Electrical Characteristics of Power IGBT According to Design and Process Parameter (설계 및 공정 변수에 따른 600 V급 IGBT의 전기적 특성 분석)

  • Kang, Ey Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.29 no.5
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    • pp.263-267
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    • 2016
  • In this paper, we analyzed the electrical characteristics of NPT planar and trench gate IGBT after designing these devices according to design and process parameter. To begin with, we have designed NPT planar gate IGBT and carried out simulation with T-CAD. Therefore, we extracted design and process parameter and obtained optimal electrical characteristics. The breakdown voltage was 724 V and The on state voltage drop was 1.746 V. The next was carried out optimal design of trench gate power IGBT. We did this research by same drift thickness and resistivity of planar gate power IGBT. As a result of experiment, we obtain 720 V breakdown voltage, 1.32 V on state voltage drop and 4.077 V threshold voltage. These results were improved performance and fabrication of trench gate power IGBT and planar gate Power IGBT.

Electrical Properties of MOS Capacitors and Transistors with in-situ doped Amorphous Si Gate (증착시 도핑된 비정질 Si 게이트를 갖는 MOS 캐패시터와 트랜지스터의 전기적 특성)

  • 이상돈;이현창;김재성;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.6
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    • pp.107-116
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    • 1994
  • In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

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Gate Location Design of an Automobile Junction Box with Integral Hinges (복합힌지를 갖는 차량용 정션박스의 게이트 위치설계)

  • 김홍석
    • Transactions of Materials Processing
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    • v.12 no.2
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    • pp.134-140
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    • 2003
  • Polymers such as polypropylene or polyethylene offer a unique feature of producing an integral hinge, which can flex over a million times without causing a failure. With such advantage manufacturing, time and cost required at the assembly stage can be eliminated by injecting the whole part as one piece. However, due to increased fluidity resistance at hinges during molding, several defects such as short shot or premature hinge failure can occur with the improper selection of gate locations. Therefore, it is necessary to optimize flow balancer in injection molding of part with hinges before actually producing molds. In this paper, resin flow patterns depending on several gate positions were investigated by numerical analyses of a simple strip part with a hinge. As a result, we found that the properly determined gate location leads to better resin flow and shorter hesitation time. Finally, injection molding tryouts using a mold that was designed one of the proposed gate systems were conducted using polypropylene that contained 20% talc. The experiment showed that hinges without defects could be produced by using the designed gate location.

An analysis of new IGBT(Insulator Gate Bipolar Transistor) structure having a additional recessedwith E-field shielding layer

  • Yu, Seung-Woo;Lee, Han-Shin;Kang, Ey-Goo;Sung, Man-Young
    • Journal of IKEEE
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    • v.11 no.4
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    • pp.247-251
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    • 2007
  • The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because there is no JFET resistance. But because of the electric field concentration in the corner of the gate edge, the breakdown voltage decreases. This paper is about the new structure to effectively improve the Vce(sat) voltage without breakdown voltage drop in 1700V NPT type recessed gate IGBT with p floating shielding layer. For the fabrication of the recessed gate IGBT with p floating shielding layer, it is necessary to perform the only one implant step for the shielding layer. Analysis on the Breakdown voltage shows the improved values compared to the conventional recessed gate IGBT structures. The result shows the improvement on Breakdown voltage without worsening other characteristics of the device. The electrical characteristics were studied by MEDICI simulation results.

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Transmission Line Analysis of Accumulation Layer in IEGT

  • Moon, Jin-Woo;Chung, Sang-Koo
    • Journal of Electrical Engineering and Technology
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    • v.6 no.6
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    • pp.824-828
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    • 2011
  • Transmission line analysis of the surface a cumulation layer in injection-enhanced gate transistor (IEGT) is presented for the first time, based on per-unit-length resistance and conductance of the surface layer beneath the gate of IEGT. Lateral electric field on the accumulation layer surface, as well as the electron current injected into the accumulation layer, is governed by the well-known wave equation, and decreases as an exponential function of the lateral distance from the cathode. Unit-length resistance and conductance of the layer are expressed in terms of the device parameters and the applied gate voltage. Results obtained from the experiments are consistent with the numerical simulations.

A New Snap-back Suppressed SA-LIGBT with Gradual Hole Injection (점진적인 홀의 주입을 통해 스냅백을 억제한 새로운 구조의 SA-LIGBT)

  • Jeon, Jeong-Hun;Lee, Byeong-Hun;Byeon, Dae-Seok;Lee, Won-O;Han, Min-Gu;Choe, Yeol-Ik
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.2
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    • pp.113-115
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    • 2000
  • The gradual hole injection LIGBT (GI-LIGBT) which employs the dual gate and the p+ injector, was fabricated for eliminating a negative resistance regime and reducing a forward voltage drop in SA-LIGBT. The elimination of the negative resistance regime is successfully achieved by initiating the hole injection gradually. Furthermore, the experimental results show that the forward voltage drop of GI-LIGBT decreases by lV at the current density of 200 $A/cm^2$, when compared with that of the conventional SA-LIGBT. It is also found that the improvement in the on-state characteristics can be obtained without sacrificing the inherent fast switching characteristics of SA-LIGBT.

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Analysis for Series Resistance of Amorphous Silicon Thin Film Transistor (비정질 실리코 박막 트랜지스터의 직렬 저항에 관한 분석)

  • Kim, Youn-Sang;Lee, Seong-Kyu;Han, Min-Koo
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.6
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    • pp.951-957
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    • 1994
  • We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.