• Title/Summary/Keyword: gate resistance

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Impact of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs

  • Kang, Min-Seok;Bahng, Wook;Kim, Nam-Kyun;Ha, Jae-Geun;Koh, Jung-Hyuk;Koo, Sang-Mo
    • Journal of Electrical Engineering and Technology
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    • v.7 no.2
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    • pp.236-239
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    • 2012
  • In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

Development of Hardware for Controlling Abnormal Temperature in PCS of Photovoltaic System (태양광발전시스템의 PCS에서 이상 온도 제어를 위한 하드웨어개발)

  • Kim, Doo-Hyun;Kim, Sung-Chul;Kim, Yoon-Bok
    • Journal of the Korean Society of Safety
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    • v.34 no.1
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    • pp.21-26
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    • 2019
  • This paper is purposed to develop hardware for controlling abnormal temperature that can occur environment and component itself in PCS. In order to be purpose, the hardware which is four part(sensing, PLC, monitoring and output) keep detecting temperature for critical components of PCS and can control the abnormal temperature. Apply to the hardware, it is selected to PV power generation facilities of 20 kW in Cheong-ju city and measured the data for one year in 2017. Through the temperature data, it is found critical components of four(discharge resistance, DC capacitor, IGBT, DSP board) and entered the setting value for operating the fan. The setting values for operating the fan are up to $130^{\circ}C$ in discharge resistance, $60^{\circ}C$ in DC capacitor, $55^{\circ}C$ in IGBT and DSP board. The hardware is installed at the same PCS(20 kW in Cheong-ju city) in 2018 and the power generation output is analyzed for the five days with the highest atmospheric temperature(Clear day) in July and August in 2017 and 2018 years. Therefore, the power generation output of the PV system with hardware increased up to 4 kWh.

Reduction of gate leakage current for AlGaN/GaN HEMT by ${N_2}O$ plasma (${N_2}O$ 플라즈마에 의한 AlGaN/GaN HEMT의 누설전류 감소)

  • Yang, Jeon-Wook
    • Journal of IKEEE
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    • v.11 no.4
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    • pp.152-157
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    • 2007
  • AlGaN/GaN high electron mobility transistors (HEMTs) were fabricated and the effect of ${N_2}O$ plasma on the electrical characteristics of the devices was investigated. The HEMT exposed to ${N_2}O$ plasma formed by 40 W of RF power in a chamber with pressure of 20 mTorr at a temperature of $200^{\circ}C$, exhibited a reduction of gate leakage current from 246 nA to 1.2 pA by 10 seconds treatment. The current between the two isolated active regions reduced from 3 uA to 7 nA and the sheet resistance of the active layer was lowered also. The variations of electrical characteristics for HEMT were occurred within a short time expose of 10 seconds and the successive expose did not influence on the improvements of gate leakage characteristics and conductivity of the active region. The reduced leakage current level was not varied by successive $SiO_2$ deposition and its removal. The transconductnace and drain current of AlGaN/GaN HEMTs were increased also by the expose to the ${N_2}O$ plasma.

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Analysis on the Noise Factors of Static Induction Photo-Transistor (SIPT) (1) - The SIPT's Equivalent Circuits for the Analysis on the Noise Factors - (정전유도(靜電誘導) 포토 트랜지스터의 잡음(雜音) 원인(原因) 분석(分析) (1) - 잡음(雜音) 원인(原因) 분석(分析)을 위한 SIPT 등가회로(等價回路) -)

  • Kim, Jong-Hwa
    • Journal of Sensor Science and Technology
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    • v.4 no.4
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    • pp.29-40
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    • 1995
  • In this paper, the noise equivalent cicuits that is necessary to the formulation of D.C. and noise characteristics, residual component and input capacitance so as to analyze on the noise factors of the SIT is proposed. The simplest noise equivalent circuit is the model representing the mechanism of the SIT and the measured values in this model were found as small as the values of the shot-noise. In the source resistance inserted equivalent circuit is conformed that the shot-noise will be reduced by the negative-feedback effect of the source resistance. In oder to analyze the correct noise reduction factor, I proposed the equivalent circuit which the formulas of the source and drain resistance was induced. In the experiment which affirm the equivalent circuits, the influence of the signal source resistance and output load resistance on the residual component is small and the residual component can be expressed by the equivalent input noise resistance. Moreover, the input capacitance is 13.6 pF when the load resistance is $0{\Omega}$ and the capacitance which does not concern with the SIT operation directly, that is, gate wire etc, is 10pF or so.

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Occurrence of Crown Gall of Rose and Rose Cultivar-specific Resistance (장미 뿌리혹병 발생과 품종간 저항성 차이)

  • Han Kyung-Sook;Kim Won-Hee;Park Jong-Han;Lee Jung-Sup;Seo Sang-Tae
    • Research in Plant Disease
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    • v.12 no.2
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    • pp.75-80
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    • 2006
  • Crown gall on rose was observed in greenhouse during year 2003-2005. The disease incidence was up to 28.3% and the disease was the severer in hydrophonics culture than that in soil. The typical gall symptom occurred mainly on the root and crown resulting in poor foliage, stunting, and fewer blossoms. Sixty-three rose cultivars were inoculated with Agrobacterium. tumefaciens isolated from rose crown gall, to evaluate rose cultivar-specific resistance. The size of galls from inoculated rose stems was measured in a greenhouse test. Tumors formed in almost varieties of rose inoculated. Based on the frequency of tumor occurrence and weight of galls formed on the stem of rose, it was shown that 'Little Marble', 'Golden Gate' and 'Rosa Rox-ette' were extremely susceptible to crown gall. Some varieties such as 'Little Silver' appeared to be resistant to the crown gall.

AC Modeling of the ggNMOS ESD Protection Device

  • Choi, Jin-Young
    • ETRI Journal
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    • v.27 no.5
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    • pp.628-634
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    • 2005
  • From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

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MOS Transistor Differential Amplifier (MOS Transistor를 이용한 착동증폭기)

  • 이병선
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.4 no.4
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    • pp.2-12
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    • 1967
  • A pair of insulated-gate metal-oxide-semiconductor field-effect transistor has been used to measure the direct current produced from the ionization chamber in the range of to A. An analisis of direct-current differential amplifier giving the expressions of the common-mode rejection ratio and the rralization of the constant-current generator to give very large effective source resistance has been presented. Voltage gain is 6.6, drift at the room temperature is 1.5mv per day. The common-mode rejection ratio is obtained maximum 84db. These facts give the feasibility of small direct-current measurements by utilizing this type transistors.

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A Study on the electrical characteristics of high voltage MOSFET with the various structure under the high temperature condition (Asymmetric 고 내압 MOSFET의 구조적 변화에 따른 고온 영역에서의 전기적 특성 분석)

  • Choi, In-Chul;Lee, Jo-Woon;Park, Tae-Su;Koo, Yong-Seo
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.579-582
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    • 2005
  • In this study, the electrical characteristic of asymmetric high voltage MOSFET (AHVMOSFET) for display IC was investigated. Measurement data are taken over range of temperature (300K-400K) and various extended drain length, and gate oxide thickness ($175{\AA}$, $350{\AA}$). In high temperature condition, drain current decreased over 30% and max transconductance deceased over 40%, and specific on-resistance increased over 30% in comparison with room temperature.

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SiC MOSFET Compared to Si Power Devices during Short Circuit Test (실리콘 카바이드와 실리콘 MOSFET의 단락회로 특성비교)

  • Nguyen, Thanh That;Ashraf, Ahmed;Park, Joung Hu
    • Proceedings of the KIPE Conference
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    • 2013.11a
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    • pp.89-90
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    • 2013
  • Higher power density, higher operational temperature, lower on state resistance and higher switching frequency capabilities of Silicon Carbide (SiC) technology devices compared to Silicon (Si) devices makes it has higher promising market. One of the most developed SiC devices is the power MOSFET. This study tests the SiC MOSFET under short circuit conditions taking into account the effect of gate voltage characteristics. The results will be compared to IGBT and MOSFET Si devices with similar ratings. A tester circuit was designed to perform the short circuit operation.

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Substrate Network Modeling and Parameter- Extraction Method for RF MOSFETs (RF MOSFET의 기판 회로망 모델과 파라미터 추출방법)

  • 심용석;강학진;양진모
    • Journal of Korea Society of Industrial Information Systems
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    • v.7 no.5
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    • pp.147-153
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    • 2002
  • In this paper, a substrate network model to be used with BSIM3 MOSFET model for submicron MOSFETs in giga hertz frequencies and its direct parameter extraction with physically meaningful values are proposed. The proposed substrate network model includes a conventional resistance and single inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed without any optimization process. The proposed modeling technique has been applied to various-sized MOS transistors. The substrate model has been validated for frequency up to 300Hz.

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