• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.129-130
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• 2008

Polycrystalline silicon (poly-Si) Schottky barrier thin film transistors (SB-TFT) are fabricated by erbium silicided source/drain for n-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs have a large on/off current ratio with a low leakage current. Moreover, the electrical characteristics of poly-Si SB TFTs are significantly improved by the additional forming gas annealing in 2 % $H_2/N_2$, because the interface trap states at the poly-Si grain boundaries and at the gate oxide/poly-Si channel decreased.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.631-634
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• 2002

In this paper we improved that hump occurrence by increased oxidation thickness, and control field oxide recess$(\leq20nm)$, wet oxidation etch time(19HF, 30sec), STI nitride wet cleaning time(99 HF, 60sec + P 90min) and gate pre-oxidation cleaning time(U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• Transactions on Electrical and Electronic Materials
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• v.2 no.3
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• pp.33-37
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• 2001

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.45-49
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• 2003

본 논문에서는 gate 산화막을 위한 Hf oxide 박막을 $Hf(dmae)_4$ (dmae=dimethylaminoethoxide) 전구체로 Direct Liquid Injection Metal Organic Chemical Vapor Deposition (DLI-MOCVD)방법을 이용하여 p-type Si(100) 기판 위에 증착하였다. 이 전구체를 이용하여 $150^{\circ}C$의 낮은 증착 온도에서도 낮은 carbon 농도와 roughness를 가지는 양질의 박막을 증착할 수 있었다. 증착된 박막은 비정질 구조를 나타내었지만 annealing 온도를 증가시킴에 따라서 결정성(monoclinic phase)을 나타내었다. $500{\AA}$으로 증착한 박막을 C-V 와 I-V curve를 통하여 전기적 특성을 평가하였다. 열처리 온도가 증가함에 따라 유효유전상수(k)는 증가하지만 열처리 온도가 $900^{\circ}C$ 이상이 되면 계면층의 형성에 의해 유효유전상수는 감소하게 되고 이에 따라 누설 전류도 감소하게 된다. 산소분위기 $800^{\circ}C$에서 annealing한 $HfO_2$ 박막의 유전상수는 20.1이고, 누설 전류 밀도는 SV에서 $2.2\times10^{-6}A/\textrm{cm}^2$ 로 좋은 전기적 특성을 가진다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.42-44
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• 2003

최근 logic 소자의 gate oxide로 기존의 $SiO_2$, SiON보다 고유전, 작은 누설전류를 가지는 물질의 개발이 중요한 이슈가 되고 있다. 본 실험실에서는 Si 기판위에 $HfO_2$ 를 바로 증착하는 경우, 기판의 Si 이박막내로 확산하여 유전율이 저하되는 문제점을 인식하고, 기판과 $HfO_2$ 사이에 $AlO_x$를 방지막으로 사용하였다. 이 때, $AlO_x$의 Al precursor 는 TMA 로 고정하고, 산화제로는 $H_2O, O_2$-plasma, O_3$ 를 각각 사용하였다. 모든 $AlO_x/HfO_y$ 박막에서 매우 우수한 누설전류특성을 얻을 수 있었는데, 특히 $O_3$ 를 산화제로 사용한 $AlO_x$ 방지막의 경우 가장 우수한 특성을 보였다. 또한 질소 분위기에서 $800^{\circ}C$ 10 분간 열처리한 후, 방지막을 사용한 모든 경우에서 보다 향상된 열적 안정성을 관찰할 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.7
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• pp.760-765
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• 1992

The material properties and the TFT characteristics fabricated on SiOS12T substrate by LPCVD using SiHS14T gas were investigated. The deposition rate showed Arrhenius behavior with an activation energy of 31Kcal/mol. And the transition temperature form amorphous to crystalline deposition was observed at 570$^{\circ}C$-580$^{\circ}C$. The strong(220) texture was observed as the deposition temperature increases. XRD analysis showed that the film texture of the as-deposited polycrystalline silicon does not change after annealing at 850$^{\circ}C$. The fabricated TFT's based on the as-deposited amorphous film showed superior electrical characteristics to those of the as-deposited polycrystalline films. It is considered that the different electrical characteristics result from the difference of flat band voltage(VS1FBT) due to the interface trap density between the gate oxide and the active channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values. So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of I$_{D}$-V$_{D}$, I$_{D}$-V$_{G}$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.ristics.