• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.321-324
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• 2001

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased packing density. This paper has compared Micro-Tec with ISE-TCAD. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths 180nm. We have presented MOSF ET's characteristics such as I-V characteristic, electric field. and compared with Micro-Tec and ISE-TCAD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.201-204
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• 2001

In this paper, for modeling of electrical characteristics in Poly Silicon Thin Film Transistors with process parameters set up optimum values, So, the I-V characteristics of poly silicon TFT parameters are examined and simulated in terms of the variations in process parameter. And these results compared and analyzed simulation values with examination value. The simulation program for characteristic analysis used SUPREM IV for processing, Matlab for modeling by mathematics, and SPICE for electric characteristic of devices. Input parameter for simulation characteristics is like condition of device process sequence, these electric characteristic of $I_D-V_D$ $I_D-V_G$, variations of grain size. The Gate oxide thickness of poly silicon are showed similar results between real device characteristics and simulation characteristics.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.56-58
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• 2005

To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.665-667
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• 2005

VIATRON TECHNOLOGIES has developed FE-RTP system that enables LTPS LCD and AMOLED manufacturers to produce poly-Si films at low cost, high throughput, and high yield. The system employs sequential heat treatment methods using temperature control and rapid thermal processor modules. The temperature control modules provide exceptionally uniform heating and cooling of the glass substrates to within ${\pm}2^a\;C$. The rapid thermal process that combines heating with field induction accelerates the treatment rates. The new FE-RTP system can process $730{\times}920mm$ glass substrates as thin as 0.4 mm. The uniform nature of poly-Si films produced by FE-RTP resulted in AMOLED panels with no laser-Muras. Furthermore, FE-RTP system also showed superior performances in other heat treatment processes involved in poly-Si TFT fabrications, such as dopant activation, gate oxide densification, hydrogenation, and pre-compaction.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1292-1297
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• 1997

본 연구에서는 latch-up 개선책의 일환으로 개발중인 매립층을 갖는 retrograde well의 형성기술과 더불어 공정 단순화를 목적으로 개발된 BILLI (Buried Implanted Layer for Lateral Isolation) well 구조[1]에 대한 공정 유기 결함을 분석하고 그에 의한 소자 열화 특성을 분석 하였으며 그 개선책을 제시 하고자 하였다. 매립층 형성에 의한 유기결함은 접합 누설전류와 Gate oxide 신뢰성을 열화 시켰으나 이온주입 후 $1000^{\circ}C$ 이상의 온도에서 10sec 정도의 RTP anneal에 의해 그 소자 특성이 개선되며 표면 결함이 감소함을 알 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.2-67.2
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• 2012

Graphene is expected to have a significant impact in various fields in the foreseeable future. For example, graphene is considered to be a promising candidate to replace indium tin oxide (ITO) as transparent conductive electrodes in optoelectronics applications. We report the tunability of the wavelength of localized surface plasmon resonance by varying the distance between graphene and Au nanoparticles [1]. It is estimated that every nanometer of change in the distance between graphene and the nanoparticles corresponds to a resonance wavelength shift of ~12 nm. The nanoparticle-graphene separation changes the coupling strength of the electromagnetic field of the excited plasmons in the nanoparticles and the antiparallel image dipoles in graphene. We also show a hysteresis in the conductance and capacitance can serve as a platform for graphene memory devices. We report the hysteresis in capacitance-voltage measurements on top gated bilayer graphene which provide a direct experimental evidence of the existence of charge traps as the cause for the hysteresis [2]. By applying a back gate bias to tune the Fermi level, an opposite sequence of switching with the different charge carriers, holes and electrons, is found [3]. The charging and discharging effect is proposed to explain this ambipolar bistable hysteretic switching.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.849-851
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께 비에 대한 문턱전압이하 스윙 및 전도중심의 변화에 대하여 분석하고자한다. 문턱전압이하 스윙은 전도중심에 따라 변화하며 전도중심은 상하단의 산화막 두께에 따라 변화한다. 비대칭 이중게이트 MOSFET는 상단과 하단의 게이트 산화막 두께를 다르게 제작할 수 있어 문턱전압이하 스윙의 저하 등 단채널효과를 감소시키기에 유용한 소자로 알려져 있다. 본 연구에서는 포아송방정식의 해석학적 해를 이용하여 문턱전압이하 스윙을 유도하였으며 상하단의 산화막두께 비가 전도중심 및 문턱전압이하 스윙에 미치는 영향을 분석하였다. 결과적으로 문턱전압이하 스윙 및 전도중심은 상하단 게이트 산화막 두께 비에 따라 큰 변화를 나타냈다. 또한 채널길이 및 채널두께, 상하단게이트 전압 그리고 도핑분포함수의 변화에 따라 문턱전압이하 스윙 및 전도중심은 상호 유기적으로 변화하고 있다는 것을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.272-277
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• 2011

The ambipolar behavior of tunneling field-effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (${\nu}$). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ${\nu}$.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.449-452
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• 2010

We have analyzed channel doping and dimensions(channel length, width and thickness) for the optimum subthreshold characteristics of DG(Double Gate) MOSFET based on the model of MicroTec 4.0. Since the DGMOSFET is the candidate device to shrink short channel effects, the determination of design rule for DGMOSFET is very important to develop sub-100nm devices for high speed and low power consumption. As device size scaled down, the controllability of dimensions and oxide thickness is very low. We have analyzed the short channel effects for the variation of channel dimensions, and found the design conditions of DGMOSFET having the optimum subthreshold characteristics for digital applications.