• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.4
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• Journal of Sensor Science and Technology
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• v.30 no.2
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• pp.114-118
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• 2021

In this study, the sensitivity of an active pixel sensor (APS) was adjusted by employing a gate/body-tied (GBT) p-channel metal-oxide semiconductor field-effect transistor (PMOSFET)-type photodetector with a transfer gate. A GBT PMOSFET-type photodetector can amplify the photocurrent generated by light. Consequently, APSs that incorporate GBT PMOSFET-type photodetectors are more sensitive than those APSs that are based on p-n junctions. In this study, a transfer gate was added to the conventional GBT PMOSFET-type photodetector. Such a photodetector can adjust the sensitivity of the APS by controlling the amount of charge transmitted from the drain to the floating diffusion node according to the voltage of the transfer gate. The results obtained from conducted simulations and measurements corroborate that, the sensitivity of an APS, which incorporates a GBT PMOSFET-type photodetector with a built-in transfer gate, can be adjusted according to the voltage of the transfer gate. Furthermore, the chip was fabricated by employing the standard 0.35 ㎛ complementary metal-oxide semiconductor (CMOS) technology, and the variable sensitivity of the APS was thereby experimentally verified.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.301.2-301.2
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• 2016

Metal-oxide thin-film transistors (TFTs) have gained a considerable interest in transparent electronics owing to their high optical transparency and outstanding electrical performance even in an amorphous state. Also, these metal-oxide materials can be solution-processed at a low temperature by using deep ultraviolet (DUV) induced photochemical activation allowing facile integration on flexible substrates [1]. In addition, high-dielectric constant (k) inorganic gate dielectrics are also of a great interest as a key element to lower the operating voltage and as well as the formation of coherent interface with the oxide semiconductors, which may lead to a considerable improvement in the TFT performance. In this study, we investigated the electrical properties of solution-processed high-k strontium-doped AlOx (Sr-AlOx) gate dielectrics. Using the Sr-AlOx as a gate dielectric, indium-gallium-zinc oxide (IGZO) TFTs were fabricated and their electrical properties are analyzed. We demonstrate IGZO TFTs with a 10-nm-thick Sr-AlOx gate dielectric which can be operated at a low voltage (~5 V).

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.941-943
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• 1999

In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.5
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• pp.992-997
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• 2016

This paper analyzes the deviation of tunneling current for the ratio of top and bottom gate oxide thickness of short channel asymmetric double gate(DG) MOSFET. The ratio of tunneling current for off current significantly increases if channel length reduces to 5 nm. This short channel effect occurs for asymmetric DGMOSFET having different top and bottom gate oxide structure. The ratio of tunneling current in off current with parameters of channel length and thickness, doping concentration, and top/bottom gate voltages is calculated in this study, and the influence of tunneling current to occur in short channel is investigated. The analytical potential distribution is obtained using Poisson equation and tunneling current using WKB(Wentzel-Kramers-Brillouin). As a result, tunneling current is greatly changed for the ratio of top and bottom gate oxide thickness in short channel asymmetric DGMOSFET, specially according to channel length, channel thickness, doping concentration, and top/bottom gate voltages.

• Proceedings of the Korea Crystallographic Association Conference
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• 2002.11a
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• pp.42-43
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• 2002

반도체 디바이스의 발전은 높은 직접화 및 동작 속도를 추구하고 있으며, 이를 위해서 MOSFET의 scale down시 발생되는 문제를 해결해야만 한다. 특히, Channel이 짧아짐으로써 발생하는 device의 열화현상으로 동작전압의 조절이 어려워 짐을 해결해야만 하며, gate oxide 두께를 줄임으로써 억제할 수 있다고 알려져 왔다. 현재, gate oxide으로 사용되고 있는 SiO2박막은 비정질로써 ～8.7 eV의 높은 band gap과 Si기판 위에서 성장이 용이하며 안정하다는 장점이 있으나, 두께가 1.6 nm 이하로 얇아질 경우 전자의 direct Tunneling에 의한 leakage current 증가와 gate impurity인 Boron의 channel로의 확산, 그리고 poly Si gate의 depletion effect[1,2] 등의 문제점으로 더 이상 사용할 수 없게 된다. 2001년 ITRS에 의하면 ASIC제품의 경우 2004년부터 0.9～l.4 nm 이하의 EOT가 요구된다고 발표하였다. 따라서, gate oxide의 물리적인 두께를 증가시켜 전자의 Tunneling을 억제하는 동시에 유전막에 걸리는 capacitance를 크게 할 수 있다는 측면에서 high-k 재료를 적용하기 위한 연구가 진행되고 있다[3]. High-k 재료로 가능성 있는 절연체들로는 A1₂O₃, Y₂O₃, CeO₂, Ta₂O, TiO₂, HfO₂, ZrO₂,STO 그리고 BST등이 있으며, 이들 재료 중 gate oxide에 적용하기 위해 크게 두 가지 측면에서 고려해야 하는데, 첫째, Si과 열역학적으로 안정하여 후속 열처리 공정에서 계면층 형성을 배제하여야 하며 둘째, 일반적으로 high-k 재료들은 유전상수에 반비례하는 band gap을 갖는 것으로 알려줘 있는데 이 Barrier Height에 지수적으로 의존하는 leakage current때문에 절연체의 band gap이 낮아서는 안 된다는 점이다. 최근 20이상의 유전상수와 ～5 eV 이상의 Band Gap을 가지며 Si기판과 열역학적으로 안정한 ZrO₂[4], HfiO₂[5]가 관심을 끌고 있다. HfO₂은 ～30의 고유전상수, ～5.7 eV의 높은 band gap, 실리콘 기판과의 열역학적 안전성 그리고 poly-Si와 호환성등의 장점으로 최근 많이 연구가 진행되고 있다. 또한, Hf은 SiO₂를 환원시켜 HfO₂가 될 수 있으며, 다른 silicide와 다르게 Hf silicide는 쉽게 산화될 수 있는 점이 보고되고 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.601-605
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• 1995

This study was concerned, after the oxide films(50 [.angs.]) were grown in a furnace and the MOS capacitor fabricated, with experimental comparison and verification about the Interference Effect of Electronic Waves in the ultra thin oxide/silicon interface. The average error was about 0.8404[%] in n'gate/p-sub and about 0.2991[%] in p$^{+}$gate/p-sub. Therefore, it was predicted that the Interference Effect of Electronic Waves can overcome somewhat according to the gate polarity.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.12-15
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• 2022

In this study, we studied the effects of transfer gate on the photocurrent characteristics of gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector. The GBT MOSFET-type photodetector has high sensitivity owing to the amplifying characteristic of the photocurrent generated by light. The transfer gate controls the flow of photocurrent by controlling the barrier to holes, thereby varying the sensitivity of the photodetector. The presented GBT MOSFET-type photodetector using a built-in transfer gate was designed and fabricated via a 0.18-㎛ standard complementary metal-oxide-semiconductor (CMOS) process. Using a laser diode, the photocurrent was measured according to the wavelength of the incident light by adjusting the voltage of the transfer gate. Variable sensitivity of the presented GBT MOSFET-type photodetector was experimentally confirmed by adjusting the transfer gate voltage in the range of 405 nm to 980 nm.