• ETRI Journal
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• 제37권6호
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• 한국전기전자재료학회논문지
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• 제15권9호
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• pp.758-763
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• 2002

A new small size Lateral Trench Electrode Insulated Gate Bipolar Transistor (LTEIGBT) is proposed and fabricated to improve the characteristics of device. The entire electrode of LTEIGBT is placed to trench type electrode. The LTEIGBT is designed so that the width of device is 19w. The latch-up current density of the proposed LTEIGBT is improved by 10 and 2 times with those of the conventional LIGBT and LTIGBT. The forward blocking voltage of the LTEIGBT is 130V. At the same size, those of conventional LIGBT and TIGBT are 60V and 100V, respectively. Because the electrodes of the proposed device is formed of trench type, the electric field in the device are crowded to trench oxide. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT and the conventional LIGBT are 80mA and 70mA, respectively, at the same breakdown voltage of 150V.

• 전기저널
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• 통권297호
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• pp.66-72
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• 2001

1957년에 사이리스터가 발표된 이래 파워반도체디바이스(이하 ''파워디바이스''라 한다)의 발전과 더불어 이것을 사용하여 전력변환$\cdot$제어와 이를 응용한 파워일렉트로닉스 산업도 현저한 발전을 이루어 왔다. 21세기를 맞이하여 지구의 유한성을 강하게 인식하고 자원과 에너지를 고도이용하는 순환형 사회에로의 전환을 도모하는 기술혁신과 IT(정보기술)를 구사한 기술보급의 움직임이 활발해지고, 파워일렉트로닉스와 그 키파트인 파워디바이스가 수행하여야 할 역할은 점점 더 중요해지고 있다. 이와 같은 배경 하에서 파워디바이스는 인버터제어를 주목적으로 사이리스터, GTO(Gate Turn-off Thyristor), 바이폴라트랜지스터, MOSFET(Metal Oxide Silicon Field Effect Transistor)에서 IGBT(Insulated Gate Bipolar Transistor)에로 진전되고, 그 응용분야도 가전제품에서 OA, 산업, 의료, 전기자동차, 전철, 전력에 이르는 폭넓은 분야로 확대되었다. 현재 파워디바이스를 취급하는 전력의 범위는 수W의 스위칭 전원에서 GW급의 직류송전까지 9단위까지에 이르러 광범위한 전력 제어가 가능하게 되었다. 한편 응용의 중심이 되는 IGBT는, 고속화와 저손실화 및 파괴 내량의 향상을 지향한 개량을 거듭하여 제5세대제품이 나타나기 시작하였다. 또한 IGBT에 구동$\cdot$보호$\cdot$진단 회로 등을 넣어 모듈화한 IPM(Intelligent Power Module)이 그 편리성과 소형화를 특징으로 파워디바이스의 주역의 자리에 정착하였다. 가전$\cdot$산업$\cdot$자동차$\cdot$전철의 각 분야에서는 시장 니즈에 최적 설계된 IPM이 개발되게 되어 보다 더한 시장확대가 기대되고 있다. 또한 종래의 Si(실리콘)에 대신하는 반도체 재료로서 SiC(실리콘 카바이드 : 탄화규소)에 대한 기대가 크고 MOSFET나 SBD 등의 파워디바이스의 조기실용화에의 대처노력도 주목할 만하다.

• 한국정보통신학회논문지
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• 제3권1호
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• pp.235-244
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• 1999

본 논문에서는 새로운 동적 컴팩션(dynamic compaction) 알고리즘을 제안하고 이용하여 CMOS 디지털 회로의 IDDQ 테스트패턴 생성한다. 제안된 알고리즘은 프리미티브 게이트 내부에서 발생하는 GOS, 브리징 고장을 검출할 수 있는 프리미티브 고장패턴을 이용하여 초기 테스트패턴을 구하고, 초기 테스트패턴에 있을 수 있는 don't care(X)의 수를 줄여 테스트 패턴의 수를 감소시킨다. 그리고 난수와 4 가지 제어도(controllability)를 사용하여 백트레이스를 수행시키는 방법을 제안한다. ISCAS-85 벤치마크 회로를 사용하여 모의 실험한 결과 큰 회로에서 기존의 정적 컴팩션 알고리즘에 비하여 45% 이상 테스트패턴 수가 감소함을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.3-6
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• 2003

This paper describes the interface stability of Ta-Mo alloy metal on $SiO_2$ Alloy was formed by co-sputtering method, and the alloy composition was varied by controlling Ta and Mo sputtering power. When the atomic composition of Ta was about 91%, the measured work function was 4.2eV that is suitable for NMOS gate. To identify interface stability between Ta-Mo alloy metal and $SiO_2$, C-V, FE-SEM(Field Emission-SEM), and XRD(X-ray diffraction) were performed on the samples annealed with rapid thermal processor between $600^{\circ}C$ and $900^{\circ}C$. Even after $900^{\circ}C$ rapid thermal annealing, excellent interface stability and electrical properties were observed. Also, thermodynamic analysis was studied to compare with experimental results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.5-6
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• 2005

High performance SiGe heterostructure metal-oxide-semiconductor field effect transistors(MOSFETs) were fabricated using well-controlled delta-doping of boron and SiGe/Si heterostructure epitaxal layers grown by reduced pressure chemical vapor deposition. In this paper, we report 1/f noise characteristics of the SiGe MOSFETs measured under various bias conditions of the gate and drain voltages changing in linear operation regions. From the noise spectral density, we found that the gate and drain voltage dependence of the noise represented same features, as usually scaled with $f^1$. However, 1/f noise was found to be much lower in the device with boron delta-doped layer, by a factor of $10^{-1}\sim10^{-2}$ in comparion with the device fabricated without delta-doped layer. 1/f noise property of delta-doped device looks important because the device may replace bipolar transistors most commonly embedded in high-frequency oscillator circuits.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.195-196
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• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.63.2-64
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• 2003

Epitaxial yttrium-stabilized HfO$_2$ thin films were deposited on p-type (100) Si substrates by pulsed laser deposition at a relatively lower substrate temperature of 550. Transmission electron microscopy observation revealed a fixed orientation relationship between the epitaxial film and Si; that is, (100)Si.(100)HfO$_2$ and [001]Si/[001]HfO$_2$. The film/Si interface is not atomically flat, suggesting possible interfacial reaction and diffusion, X-ray photoelectron spectrum analysis also revealed the interfacial reaction and diffusion evidenced by Hf silicate and Hf-Si bond formation at the interface. The epitaxial growth of the yttrium stabilized HfO$_2$ thin film on bare Si is via a direct growth mechanism without involoving the reaction between Hf atoms and SiO$_2$ layer. High-frequency capacitance-voltage measurement on an as-grown 40-A yttrium-stabilized HfO$_2$ epitaxial film yielded an dielectric constant of about 14 and equivalent oxide thickness to SiO$_2$ of 12 A. The leakage current density is 7.0${\times}$ 10e-2 A/$\textrm{cm}^2$ at 1V gate bias voltage.

• 한국전기전자재료학회논문지
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• 제36권4호
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• pp.413-417
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• 2023

Gallium Oxide (Ga₂O₃) is preferred as a material for next generation power semiconductors. The Ga₂O₃ should solve the disadvantages of low thermal resistance characteristics and difficulty in forming an inversion layer through p-type ion implantation. However, Ga₂O₃ is difficult to inject p-type ions, so it is being studied in a heterojunction structure using p-type oxides, such as NiO, SnO, and Cu₂O. Research the lateral-type FET structure of NiO/Ga₂O₃ heterojunction under the Gate contact using the Sentaurus TCAD simulation. At this time, the VG-ID and VD-ID curves were identified by the thickness of the Epi-region (channel) and the doping concentration of NiO of 1×10¹⁷ to 1×10¹⁹ cm-3. The increase in Epi region thickness has a lower threshold voltage from -4.4 V to -9.3 V at I_D = 1×10^-8 mA/mm, as current does not flow only when the depletion of the PN junction extends to the Epi/Sub interface. As an increase of NiO doping concentration, increases the depletion area in Ga₂O₃ region and a high electric field distribution on PN junction, and thus the breakdown voltage increases from 512 V to 636 V at I_D =1×10^-3 A/mm.

• 한국재료학회지
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• 제12권2호
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.