• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.31-39
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• 2001

W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

• Restorative Dentistry and Endodontics
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• v.19 no.2
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• pp.611-620
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• 1994

The purpose of this study was to evaluate the effect of post space preparation on apical sealing according to the methods and time of gutta percha removal. Forty six extracted single rooted teeth were selected for this study. Forty teeth were used as experimental groups and six teeth as control groups. Forty teeth were routinely prepared by step-back method and obturated with gutta percha cones and zinc oxide-eugenol cement using lateral condensation. All obturated teeth were divided into 4 groups of 10 teeth each. In each group of 1, 2, 3, heated plugger, gate glidden drill and chloroform and K-file were used respectively for post space preparation by removing the gutta percha immediately after obturation. In group 4, post space were prepared with gate glidden drill one week after obturation. In all experimental groups, the post space were prepared so that 4mm of apical gutta percha remained. After post space preparation, apical leakage were measured with electrochemical method for 28 days and analyzed statistically. The following results were obtained ; 1. No statistically significant differences in apical leakage were occured among the experimental groups using heated plugger, gate glidden drill and chloroform and K-file to remove the gutta percha immediately after obturation. 2. No significant difference in apical leakage was found between the teeth prepared post space immediately after obturation and those prepared 1 week after obturation. 3. In all experimental groups, the apical leakage was increased with time passage regardless of the post space preparation time and the gutta percha removal techniques.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.263-266
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• 2003

The gate leakage current is first calculated using the experimental method between gate and drain by opening source electrode. Next, the gate to drain current has been obtained with a ground source. The difference of two current has been tested and provide that the existence of another source to Schotuy barrier height against the image force lowering effect.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.350-350
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• 2012

본 연구에서는 Oxide 두께가 각각 4, 6 nm인 Symmetric NMOSFET의 전기적 특성 분석에 관한 연구를 진행하였다. 게이트 전압에 따른 Drain saturation current (IDSAT), Threshold Voltage(VT) 및 드레인 전압에 따른 Off-states 특성 변화를 분석하였다. 소자 측정 결과 oxide 두께가 4 nm인 경우 Vt는 0.3 V, IDSAT은 73 ${\mu}A$ (@VD=0.05)로, oxide 두께가 6 nm인 경우 Vt는 0.65 V, IDSAT은 66 ${\mu}A$ (@VD=0.05)로 각각 측정되었다. 이는 oxide 두께가 얇은 경우 게이트 전압 인가 시 Electric field 증가에 따른 것으로 판단된다. 또한 드레인 전압 인가에 따른 소자 특성 분석 결과 oxide 두께가 4nm인 경우 급격한 Gate leakage 증가를 보였으며, 이에 따라 Off-state에서의 leakage current가 증가함을 확인하였다. 본 연구는 Oxide 두께에 따른 MOSFET 소자의 전기적 특성 분석을 위해 진행되었으며, 상기 결과와 같이 oxide 두께 가변은 Idsat, Vt, leakage current 등의 주요 파라미터에 영향을 주어 NMOSFET 소자의 전기적 특성을 변화시킴을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• KEPCO Journal on Electric Power and Energy
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• v.2 no.2
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• pp.223-225
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• 2016

The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.138-138
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• 2017

차세대 CMOS 소자의 지속적인 고직접화를 위해서는 높은 gate capacitance와 낮은 gate leakage current를 확보를 위한, 적절한 metal gate electrode와 high-k dielectric 물질의 개발이 필수적으로 요구된다. 특히, gate dielectric으로 적용하기 위한 다양한 high-k dielectric 물질 후보군 중에서, 높은 dielectric constant와, 낮은 leakage current, 그리고 Si과의 우수한 열적 안정성을 가지는 Zr silicates 또는 Hf silicates(ZrSiO4와 HfSiO4) 물질이 높은 관심을 받고 있으며, 이를 원자층 증착법을 통해 구현하기 위한 노력들이 있어왔다. 그러나, 현재까지 보고된 원자층 증착법을 이용한 Zr silicates 및 Hf silicates 공정의 경우, 개별적인 Zr(또는 Hf)과 Si precursor를 이용하여 ZrO2(또는 HfO2)과 SiO2를 반복적으로 증착하는 방식으로 Zr silicates 또는 Hf silicates를 형성하고 있어, 전체 공정이 매우 복잡해지는 문제점 뿐 아니라, gate dielectric 내에서 Zr과 Si의 국부적인 조성 불균일성을 야기하여, 제작된 소자의 신뢰성을 떨어뜨리는 문제점을 나타내왔다. 따라서, 본 연구에서는 이러한 문제점을 개선하기 위하여, 하나의 precursor에 Zr (또는 Hf)과 Si 원소를 동시에 가지고 있는 DNS-Zr과 DNS-Hf bimetallic precursor를 이용하여 새로운 ZrSiO4와 HfSiO4 ALD 공정을 개발하고, 그 특성을 살펴보고자 하였다. H2O와 O3을 reactant로 사용한 원자층 증착법 공정을 통하여, Zr:Si 또는 Hf:Si의 화학양론적 비율이 항상 일정한 ZrSiO4와 HfSiO4 박막을 형성할 수 있었으며, 이들의 전기적 특성 평가를 진행하였으며, dielectric constant 및 leakage current 측면에서 우수한 특성을 나타냄을 확인할 수 있었다. 이러한 결과를 바탕으로, bimetallic 전구체를 이용한 ALD 공정은 차세대 고성능 논리회로의 게이트 유전물질에 응용이 가능할 것으로 판단된다.