• Title/Summary/Keyword: gate electrode

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Surface Treatment Effect on Electrical Characteristics of Ink-Jet Printed Pentacene OTFTs Employing Suspended Source/Drain Electrode

  • Park, Young-Hwan;Kim, Yong-Hoon;Kang, Jung-Won;Oh, Myung-Hwan;Han, Jeong-In
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08b
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    • pp.1312-1314
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    • 2007
  • The effect of gate insulator surface treatment on electrical characteristics of bottom contact (BC) and suspended source/drain (SSD) organic thinfilm transistors (OTFTs) was studied. Triisopropylsilylethynyl pentacene was used as an active material and was printed by ink-jet printing method. In case of the BC OTFTs, threshold voltage was shifted from positive to near zero, and the fieldeffect mobility was increased when the gate insulator surface was treated with hexamethyldisilazane. However, in case of SSD OTFT, threshold voltage shift was not observed and the field-effect mobility was decreased.

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Antireflective ZTO/Ag bilayer-based transparent source and drain electrodes for highly transparent thin film transistors

  • Choe, Gwang-Hyeok;Kim, Han-Gi
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2012.05a
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    • pp.110.2-110.2
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    • 2012
  • We reported on antireflective ZnSnO (ZTO)/Ag bilayer and ZTO/Ag/ZTO trilayer source/drain (S/D) electrodes for all-transparent ZTO channel based thin film transistors (TFTs). The ZTO/Ag bilayer is more transparent (83.71%) and effective source/drain (S/D) electrodes for the ZTO channel/Al2O3 gate dielectric/ITO gate electrode/glass structure than ZTO/Ag/ZTO trilayer because the bottom ZTO layer in the trilayer increasea contact resistance between S/D electrodes and ZTO channel layer and reduce the antireflection effect. The ZTO based all-transparent TFTs with ZTO/Ag bilayer S/D electrode showed a saturation mobility of 4.54cm2/Vs and switching property (1.31V/decade) comparable to TTFT with Ag S/D electrodes.

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Design and fabrication of a Micromechanical Switch Using Polysilicon Surface Micromachining (다결정실리콘 표면 미세가공 기술을 이용한 초소형 기계식 스위치의 설계 및 제작)

  • Chae, Gyeong-Su;Han, Seung-O;Ha, Jong-Min;Mun, Seong-Uk;Park, Jeong-Ho
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.9
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    • pp.546-551
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    • 2000
  • A micromechanical switch that can be used as a logic gate is described in this paper. This switch consists of fixed input electrodes an output electrode Vcc/GND electrodes and movable plates suspended by crab-leg flexures. for mechanical switching of an electrical signal a parallel plate actuator which comes in contact with output electrode was used. Provided that movable plates are connected to Vcc and a low input voltage(ground signal) is applied to the fixed input electrodes the movable plates are pulled by an electrostatic force between the fixed input electrodes and the movable plates. the proposed micromechanical switch was fabricated by surface micromachining technology with$2\mum$ -thick poly-Si and the measured threshold voltage for ON/OFF switching was 23.5V.

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Fabrication of wrap-around gate nanostructures from electrochemical deposition (전기화학적 도금을 이용한 wrap-around 게이트 나노구조의 제작)

  • Ahn, Jae-Hyun;Hong, Su-Heon;Kang, Myung-Gil;Hwang, Sung-Woo
    • Journal of IKEEE
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    • v.13 no.2
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    • pp.126-131
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    • 2009
  • To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.

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The Delay-Time Characteristics of DC Discharge in the Discharge Logic Gate Plasma Display Panel (방전논리게이트 플라즈마 디스플레이 패널의 직류방전 지연특성)

  • Ryeom, Jeong-Duk;Kwak, Hee-Ro
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.1
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    • pp.28-34
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    • 2007
  • In this research, the characteristics of the DC discharge that was the logical gate input of discharge logic gate PDP newly proposed was considered. The logical output is induced by controlling the potential difference of inter-electrode according to the discharge path in the discharge logic gate. From the experimental result the discharge time lag was shortened to 1/3 and the voltage has decreased to 1/2 in the case to apply priming discharge for improving stability of these DC discharges compared with the case when it is not applied. Moreover, after the priming discharge ends, the space charge generated by this discharge influences it up to about $30[{\mu}s]$. And, as a measured result of the influence that the space charge exerts on the DC discharge with the change in time and spatial distance, it has been understood that there is a possibility that going away spatially can slip out the influence of the discharge easily as for going away from the discharge time-wise. Therefore the conclusion that the discharge logic gates of each scanning electrode can be operated independently is obtained.

Thermal Stability and Electrical Properties of HfOxNy Gate Dielectrics with TaN Gate Electrode

  • Kim Jeon-Ho;Choi Kyu-Jeong;Seong Nak-Jin;Yoon Soon-Gil;Lee Won-Jae;Kim Jin-dong;Shin Woong-Chul;Ryu Sang-Ouk;Yoon Sung-Min;Yu Byoung-Gon
    • Transactions on Electrical and Electronic Materials
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    • v.4 no.3
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    • pp.34-37
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    • 2003
  • [ $HfO_2$ ] and $HfO_xN_y$ films were deposited by plasma-enhanced chemical vapor deposition using $Hf[OC(CH_3)_3]_4$ as the precursor in the absence of $O_2$. The crystallization temperature of the $HfO_xN_y$ films is higher than that of the $HfO_2$ film. Nitrogen incorporation in $HfO_xN_y$ was confirmed by auger electron spectroscopy analysis. After post deposition annealing (PDA) at 800$\Box$, the EOT increased from 1.34 to 1.6 nm in the $HfO_2$ thin films, whereas the increase of EOT was suppressed to less than 0.02 nm in the $HfO_xN_y$. The leakage current density decreased from 0.18 to 0.012 $A/cm^2$ with increasing PDA temperature in the $HfO_2$ films. But the leakage current density of $HfO_xN_y$ does not vary with increasing PDA temperature because an amorphous $HfO_xN_y$ films suppresses the diffusion of oxygen through the gate dielectric.

Thermal Stability and Electrical Properties of $HfO_xN_y$ ($HfO_2$) Gate Dielectrics with TaN Gate Electrode (TaN 게이트 전극을 가진 $HfO_xN_y$ ($HfO_2$) 게이트 산화막의 열적 안정성)

  • Kim, Jeon-Ho;Choi, Kyu-Jeong;Yoon, Soon-Gil;Lee, Won-Jae;Kim, Jin-Dong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.54-57
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    • 2003
  • [ $HfO_xN_y$ ] films using a hafnium tertiary-butoxide $(Hf[OC(CH_3)_3]_4)$ in plasma and $N_2$ ambient were prepared to improve the thermal stability of hafnium-based gate dielectrics. A 10% nitrogen incorporation into $HfO_2$ films showed a smooth surface morphology and a crystallization temperature as high as $200^{\circ}C$ compared with pure $HfO_2$ films. The $TaN/HfO_xN_y/Si$ capacitors showed a stable capacitance-voltage characteristics even at post-metal annealing temperature of $1000^{\circ}C$ in $N_2$ ambient and a constant value of 1.6 nm EOT (equivalent oxide thickness) irrespective of an increase of PDA and PMA temperature. Leakage current densities of $HfO_xN_y$ capacitors annealed at PDA temperature of 800 and $900^{\circ}C$, respectively were approximately one order of magnitude lower than that of $HfO_2$ capacitors.

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A Research About P-type Polycrystalline Silicon Thin Film Transistors of Low Temperature with Metal Gate Electrode and High Temperature with Gate Poly Silicon (실리콘 게이트전극을 갖는 고온소자와 금속 게이트전극을 갖는 P형 저온 다결정 실리콘 박막 트랜지스터의 전기특성 비교 연구)

  • Lee, Jin-Min
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.6
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    • pp.433-439
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    • 2011
  • Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

Printing Technologies for the Gate and Source/Drain Electrodes of OTFTs

  • Lee, Myung-Won;Lee, Mi-Young;Song, Chung-Kun
    • Journal of Information Display
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    • v.10 no.3
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    • pp.131-136
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    • 2009
  • This is a report on the fabrication of a flexible OTFT backplane for electrophoretic display (EPD) using a printing technology. A practical printing technology for a polycarbonate substrate was developed by combining the conventional screen and inkjet printing technologies with the wet etching and oxygen plasma processes. For the gate electrode, the screen printing technology with Ag ink was developed to define the minimum line width of ${\sim}5{\mu}m$ and the thickness of ${\sim}70nm$ with the resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, which are suitable for displays with SVGA resolution. For the source and drain (S/D) electrodes, PEDOT:PSS, whose conductivity was drastically enhanced to 450 S/cm by adding 10 wt% glycerol, was adopted. In addition, the modified PEDOT:PSS could be neatly confined in the specific S/D electrode area that had been pretreated with oxygen. The OTFTs that made use of the developed printing technology produced a mobility of ${\sim}0.13cm^2/Vs.ec$ and an on/off current ratio of ${\sim}10^6$, which are comparable to those using thermally evaporated Au for the S/D electrode.

Development of a Micro pH-ISFET Probe for in vivo Measurements of the Ion Concentration in Blood (생체내의 혈중이온농도 예측을 위한 마이크로 pH-ISFET프로브의 개발)

  • Sohn, Byung-Ki;Lee, Jong Hyun;Lee, Kwang Man
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.1
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    • pp.83-90
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    • 1986
  • A micro pH-ISFET probe, which can be applied to the in vivo measurements of the hydrogen ion concentration in blood, has been developed, and a measuring system equiped with this probe also developed. The pH-ISFET has been fatricated by employing the techniques of integrated circuit fabrication. Two kinds of micro electrode formed around the sensing gate during the wafer process, and the other is a capillary type of Ag/AfCl/sat. KCI reduced in size. This capillary electrode has shown its good performance characteristics so far in the application with ISFET as well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and well as a commercial one. In order to form a micro pH-ISFET probe, this pH-ISFET and the capillary electrode were built together into a needle tip having 1 mm inner diameter. The chip size of a twin pH-ISFET is 0.8 mmx1.4 mm, the material of the sensing gate membrane is Si3N4, and the sensitivity of the developed probe is about 52mV/pH.

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