• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.346-349
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• 1996

In application of high power IGBT PWM inverters, the treatable power range is considerably limited due to the overvoltage caused by the stray inductance components within the power circuit. This paper proposes a new gate drive circuit for IGBTs which can actively suppress the overvoltage across the driven IGBT at turn-off and the overvoltage across the opposite IGBT at turn-on while preserving the most simple and reliable power circuit. The turn-off driving scheme has adaptive feature to the amplitude of collector current, so that the overvoltage is limited much effectively at the larger collector current. The turn-on scheme is to decrease the rising rate of the collector current by increasing input capacitance during turn-on transient when the gate-emitter voltage is greater than threshold voltage. The experimental results under various normal and fault conditions prove the effectiveness of the proposed circuit.

• Journal of Power Electronics
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• v.14 no.2
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.741-743
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• 2004

In this paper, we describe a Control Element Drive Mechanism(CEDM) operation test using a Power Controller. By testing, we can catch the mechanical and electrical characteristics of CEDM and obtain the information about the improvement of CEDM and the design of CEDM power cabinet. The power controller for CEDM introduced in this paper can input firing angles directly into gate drive circuits of thyristors so that this method can be used to derive the maximum and minimum values of firing angles within available limits for a 3-phase half-wave rectifier. Angle inputs help us understand each coil's response characteristics. Since this power controller generates a serial sequence for CEDM insertion and withdrawal operations, we may judge whether CEDM works correctly as expected or not in each phase of a step movement.

• Journal of the Korean Society of Safety
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• v.29 no.1
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• pp.7-14
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• 2014

Inverter module, which feeds the converted power to the traction motor for EMU. Consists of the power semiconductors with their gate drive unit(GDU)s and the control computer for driving, voltage, current and speed controls. Electrolytic condenser, connected to the gate drive unit and a core component to drive the power semiconductor, has problems such as reduction in lifetime and malfunction caused by electrical and mechanical characteristic changes from heat generation during high speed switching for generation of stable power. In this study, To check the service life of electrolytic condenser, the test was carried out in two ways. First, In the case of accelerated life testing of condenser, the Arrhenius model is a way of life testing. Another way is to analyze the reliability of the failure data by the method of parametric data analysis. Eventually, life time by accelerated life test than a method of failure data analysis(Weibull distribution) was found to be slightly larger output.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1847-1853
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• 2014

The PAPR of the input signal is increased due to OFDMA signal in a mobile communication system. High efficiency of a power amplifier, which accounts for power consumption, is a very important key technology. Digital Pre-Distortion techniques were used to improve the linearity of the power amplifier. The Asymmetric Doherty scheme was used to improve the efficiency of the power amplifier. In this paper, we propose a new structure of Asymmetric Doherty. Drive power amplifier part is separated as main path and peak path, and phase shifter is employed to improve power combine characteristics of the Doherty Amplifier. Also, envelope tracking technology for drive gate bais in drive peak amplifier is used to improve efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.58-65
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• 2009

In this paper, we designed high voltage gate drive IC including dead time circuit in which capacitors controlled rising time and falling time, and schimitt-triggers controlled switching voltage. Designed High voltage gate drive IC improves an efficiency of half-bridge converter by decreasing dead time variation against temperature and has variable dead time by the capacitor value. and its power dissipation, which is generated on high side part level shifter, has decreased 52 percent by short pulse generation circuit, and UVLO circuit is designed to prevent false-operation. We simulated by using Spectre of Cadence to verify the proposed circuit and fabricated in a 1.0um process.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.560-576
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• 2018

• Journal of IKEEE
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• v.25 no.2
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• pp.381-387
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• 2021

As Head-Mounted Displays(HMDs), which are mainly used to maximize realism in games and videos, have experienced increased demand and expanded scope of use in education and training, there is growing interest in methods to enhance the performance of conventional HMDs. In this study, a methodology to utilize Carbon NanoTubes(CNTs) to improve the performance of gate drivers that send control signals to each pixel circuit of the HMD is discussed. This paper proposes a new circuit design method that replaces the transistors constituting the buffer part of the conventional gate driver with transistors incorporating CNTs and compare the performance of the suggested gate drive with that of a gate driver comprising only conventional transistors via simulations. According to the simulation results, by including CNTs in the gate driver, the output voltage can be increased by approximately 0.3V compared to the conventional gate driver high voltage(1.1V) at a speed of 12.5 GHz and the gate width also can be reduced by up to 20 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.919-921
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• 1995

In this paper, development of Thermal Printer Head(TPH) controller by using gate array having high reliability and good performance is proposed. Over the 3000 gates are performed to control print image data signals and relative peripheral hardwares. The proposed gate array has TPH control circuit, print control and step motor drive, and print image data control, decoder output control parts. This TPH controller will be a good application to FAX or label printer and barcode printers.