• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.346-349
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• 1996

In application of high power IGBT PWM inverters, the treatable power range is considerably limited due to the overvoltage caused by the stray inductance components within the power circuit. This paper proposes a new gate drive circuit for IGBTs which can actively suppress the overvoltage across the driven IGBT at turn-off and the overvoltage across the opposite IGBT at turn-on while preserving the most simple and reliable power circuit. The turn-off driving scheme has adaptive feature to the amplitude of collector current, so that the overvoltage is limited much effectively at the larger collector current. The turn-on scheme is to decrease the rising rate of the collector current by increasing input capacitance during turn-on transient when the gate-emitter voltage is greater than threshold voltage. The experimental results under various normal and fault conditions prove the effectiveness of the proposed circuit.

• Journal of Power Electronics
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• 제14권2호
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.741-743
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• 2004

In this paper, we describe a Control Element Drive Mechanism(CEDM) operation test using a Power Controller. By testing, we can catch the mechanical and electrical characteristics of CEDM and obtain the information about the improvement of CEDM and the design of CEDM power cabinet. The power controller for CEDM introduced in this paper can input firing angles directly into gate drive circuits of thyristors so that this method can be used to derive the maximum and minimum values of firing angles within available limits for a 3-phase half-wave rectifier. Angle inputs help us understand each coil's response characteristics. Since this power controller generates a serial sequence for CEDM insertion and withdrawal operations, we may judge whether CEDM works correctly as expected or not in each phase of a step movement.

• 한국안전학회지
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• 제29권1호
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• pp.7-14
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• 2014

Inverter module, which feeds the converted power to the traction motor for EMU. Consists of the power semiconductors with their gate drive unit(GDU)s and the control computer for driving, voltage, current and speed controls. Electrolytic condenser, connected to the gate drive unit and a core component to drive the power semiconductor, has problems such as reduction in lifetime and malfunction caused by electrical and mechanical characteristic changes from heat generation during high speed switching for generation of stable power. In this study, To check the service life of electrolytic condenser, the test was carried out in two ways. First, In the case of accelerated life testing of condenser, the Arrhenius model is a way of life testing. Another way is to analyze the reliability of the failure data by the method of parametric data analysis. Eventually, life time by accelerated life test than a method of failure data analysis(Weibull distribution) was found to be slightly larger output.

• 한국정보통신학회논문지
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• 제18권8호
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• pp.1847-1853
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• 2014

이동통신 시스템의 OFDMA 방식은 신호에 대한 PAPR(Peak to Average Power Ratio) 값의 증가를 가져왔다. 이동통신 시스템 전력 소모의 대부분을 차지하는 전력 증폭기에 대한 효율 개선은 매우 중요한 핵심 기술이다. 전력 증폭기의 선형 특성 개선을 위해 디지털전치왜곡 기술을 사용하였으며, 전력 증폭기의 효율 개선을 위해 비대칭 도허티(Asymmetric Doherty) 방식을 사용하였다. 본 논문에서는 기존 비대칭 도허티 구조와 다른 새로운 구조의 비대칭 도허티 구조를 제안하였다. 제안하는 새로운 구조의 비대칭 도허티 방식에서는 전력 증폭기 구동단을 주경로와 첨두경로로 분리하였으며, 위상 변환기를 이용하여 도허티 증폭기의 전력 결합 특성을 개선하였다. 또한 구동단 첨두 증폭기 gate bais에 대한 포락선 추적 기술을 적용하여 효율을 개선하였다.

• 대한전자공학회논문지SD
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• 제46권12호
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• pp.58-65
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• 2009

본 논문에서는 캐패시터로 상승 시간과 하강 시간을 조절하고 슈미트 트리거의 스위칭 전압을 이용한 데드 타임 회로를 갖는 고전압 구동 IC (High Voltage Gate Driver IC)를 설계하였다. 설계된 고전압 구동 IC는 기존 회로와 비교하여 온도에 따 른 데드 타임 변동을 약 52% 줄여 하프브리지 컨버터의 효율을 증대시켰으며 캐패시터 값에 따라 가변적인 데드 타임을 가진다. 또한 숏-펄스 (short-pulse) 생성회로를 추가하여 상단 레벨 쉬프트 (High side part Level shifter)에서 발생하는 전력소모를 기존의 회로에 비해 52% 감소 시켰고, UVLO를 추가하여 시스템의 오동작을 방지하여 시스템의 안정도를 향상시켰다. 제안한 회로를 검증하기 위해 Cadence의 Spectre을 이용하여 시뮬레이션 하였고 1.0um 공정을 이용하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.560-576
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• 2018

• 전기전자학회논문지
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• 제25권2호
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• pp.381-387
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• 2021

과거 주로 게임과 동영상 재생에 있어 리얼함을 극대화하기 위해 사용되었던 HMD(Head Mount Display)의 수요가 증가하고, 그 활용 범위가 교육과 훈련 등으로 확대되면서, 기존 HMD의 성능을 향상시킬 수 있는 방안에 대한 관심이 높아지고 있다. 본 논문에서는 HMD의 각 화소 회로에 제어 신호를 보내는 gate driver의 성능을 향상시키기 위해 CNT를 포함한 트랜지스터를 활용하는 방법에 대해 논하고자 한다. 기존 gate driver의 버퍼부를 구성하는 트랜지스터를 CNT를 포함한 트랜지스터로 교체하는 회로 설계 방법을 제안하고, 그 성능을 회로 시뮬레이션을 통해 기존 트랜지스터로만 구성된 gate driver의 성능과 비교해 보고자 한다. 시뮬레이션 결과, gate driver에 CNT를 포함할 경우 12.5 GHz의 속도로 기존 gate driver 대비 약 0.3V 증가된 출력 전압(1.1V)을 얻을 수 있었으며, 최대 20배의 gate width를 줄일 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권3호
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 B
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• pp.919-921
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• 1995

In this paper, development of Thermal Printer Head(TPH) controller by using gate array having high reliability and good performance is proposed. Over the 3000 gates are performed to control print image data signals and relative peripheral hardwares. The proposed gate array has TPH control circuit, print control and step motor drive, and print image data control, decoder output control parts. This TPH controller will be a good application to FAX or label printer and barcode printers.