• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.693-695
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• 2003

In this paper, we have investigated temperature-dependent characteristics of current-voltage for double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated the temperature-dependent characteristics of current-voltage and drain voltage is changed from 0V to 5.0V at $V_{mg}$ =1.5V and $V_{sg}$ =3.0V. We have obtained a very good characteristics of current-voltage for 77K. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.27-31
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• 2004

Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated $I_G-V_G$ of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.379-382
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• 2002

GaAs has wide band gap, Therefore that malarial can used high Temperature application. in this paper explain to current-voltage characteristics of thermal effect. we experiment on thermal test of current-voltage characteristics and gate leakage current with real device. As a result, we propose a current-volatage characteristics model. that model base on gate leakage current, and gate leakage current influence gate source voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.955-960
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• 2007

In this paper, the deviation of tunneling current for gate voltage has been investigated in double gate MOSFET developed to decrease the short channel effects. In device scaled to nano units, the tunneling current is very important current factor and rapidly increases,compared with thermionic emission current according to device size scaled down. We consider the change of tunneling current according to gate voltage in this study. The potential distribution is derived to observe the change of tunneling current according to gate voltage, and the deviation of off-current is derived from the relation of potential distribution and tunneling probability. The derived current is compared with the termionic emission current, and the relation of effective gate voltage to decrease tunneling current is obtained.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.884-886
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• 2005

In this paper, we have investigated characteristics of current-voltage for double gate MOSFET with main gate and side gate. Investigated current-voltage characteristics of channel length changed len호 of channel from 1${\mu}$m to 3${\mu}$m. Also, compare and analyzed characteristics of changed of operation temperature changing current that is dignity. gate voltage could know 2V that is superior than device characteristics of current voltage characteristic in 77K acts in room temperature when approved.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.56-62
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• 2003

In this paper, we designed a adder and a multiplier using current mode T-gate on $GF(2^2)$. The T-gate is consisted of current mirror and pass transistor, the designed 4-valued T-gate used adder and multiplier on $GF(2^2)$. We designed its under 1.5um CMOS standard technology. The unit current of the circuits is 15㎂, and power supply is 3.3V VDD. The proposed current mode CMOS operator have a advantage of module by T-gate`s arrangement, and so we easily implement multi-valued operator.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1101-1104
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• 2003

In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1333-1335
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• 2000

In order to turn on the SCR gate, trigger signal source have to provide appropriate gate current and voltage under the gate rating based on the characteristic of SCR, the nature of load and power. It will be essential design factors such as trigger source impedance, trigger signal occurring, signal time width and turn off conditions. Also minimum gate trigger current is changed with the deterioration of SCR. SCR, which is needed large gate trigger current absolutely, is very important for SCR characteristic test because it causes unstable output in the misfile or makes a trouble to pulse trigger circuits. This paper shows scheme to test the performance of SCR with the precision analyzing mechanism and the changing trend of minimum gate current under the trigger conditions.