• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.331-341
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• 2013

In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

• Journal of Sensor Science and Technology
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• v.16 no.2
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• pp.104-109
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• 2007

In this paper, we have fabricated on extended-gate field effect transistor (EGFET)-type protein sensor for the application to a CRP detection. We used the self-assembled monolayer (SAM) to adhere or entrap biomolecules, namely CRP antibodies. The experimental result shows that the proposed SAM is well immobilized on the gold gate surface. So the drain current was varied by antigen-antibody interactions on the gate surface because of the CRP charge. Experimental results related to the formation of SAM, antibody, antigen were obtained by measuring the electrical characteristics of the EGFET device.

• Journal of IKEEE
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• v.22 no.2
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• pp.484-487
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• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.1943-1950
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• 2009

The development of high voltage Insulated Gate Bipolar Transistor (IGBT) have given new device advantage in the areas where they compete with conventional GTO (Gate Turnoff Thyristor) technology. The IGBT combines the advantages of a power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) and a bipolar power transistor. The change of electrical characteristics for IGBT is mainly coming from the change of characteristics of MOSFET at the input gate and the PNP transistors at the output. The gate oxide structure gives the main influence on the changes in the electrical characteristics affected by environments such as radiation and temperature, etc.. The change of threshold voltage, which is one of the important design parameters, is brought by charge trapping at the gate oxide. In this paper, the electrical characteristics are simulated by SPICE simulation, and the parameters are found to design optimized circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.152-159
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• 2010

We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-back Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.34 no.5
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• pp.109-118
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• 2018

Noryang Temporary Palace was a place where king Jeongjo (1752-1800) would have lunch after crossing the Temporary Palace River on his way to Hwaseong Temporary Palace to worship at Hyeonryungwon, the tomb of his father, Sadoseja. The government offices in charge of ship bridge construction 'Jugyosa' and 'Byeoljangso' were located in the Temporary Palace. The central buildings of the Haenggung Palace, which ranged up to Yongyangbongjeojeong, were arranged to observe both 'Jugyosa' and 'Byeoljangso' from the Temporary Palace by lifting the ground from Sammun Gate to Yongyangbongjeojeong. Yongyangbongjeojeong, the center of Noryang Temporary Palace, features the style of royal palace architecture and functions of housing architecture. The 'Jugyosa' and 'Byeoljangso' buildings had eight quarters. According to the records, in addition, 15 wood sheds, 5 rice hubs, 3 barns, 1 side gate quarter, 1 front gate, 70 separate sheds, 2 suragan temporary buildings, oesammun gate and hongsalmun gate were found. Such architectural layout is matched with the Temporary Palace Jugyohwaneodo Painting.

• Journal of Electrical Engineering and Technology
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• v.1 no.2
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• pp.233-236
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• 2006

A 3-D numerical simulation of a buried-channel CCD (Charge Coupled Device) with a deep depletion has been performed to investigate its electrical and physical behaviors. Results are presented for a deep depletion CCD (EEV CCD12; JET-X CCD) fabricated on a high-resistivity $(1.5k\Omega-cm)\;65{\mu}m$ thick epi-layer, on a $550{\mu}m$ thick p+ substrate, which is optimized for X-ray detection. Accurate predictions of the Potential minimum and barrier height of a CCD Pixel as a function of mobile electrons are found to give good charge transfer. The depletion depth approximation as a function of gate and substrate bias voltage provided average errors of less than 6%, compared with the results estimated from X-ray detection efficiency measurements. The result obtained from the transient simulation of signal charge movement is also presented based on 3-Dimensional analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.433-436
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• 1999

In this paper we applied TVS(Triangular Voltage Sweep) method to calculate the mobile ionic charge densities in some ferroelectric thin films. During the measurement, the temperature of specimens were maintained at 20$0^{\circ}C$. By this method, the amount of mobile ionic charge Q$_{m}$ and mobile ionic charge density N$_{m}$ of a MFIS structure were calculated 3.5 [pC] and about 4.3$\times$10$^{11}$ [ions/cm$^2$], respectively. In order to successful TVS measurement, the gate leakage current density of films must be low 10$^{-9}$ (A/cm$^2$) order.der.

• Korean Journal of Metals and Materials
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• v.48 no.3
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• pp.256-261
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• 2010

In this work, high-k dielectric stacks of $HfO_2$ and $HfO_2$/$Al_2O_3$/$HfO_2$ (HAH) were deposited on $SiO_2/Si$ substrates by atomic layer deposition as charge trapping layers in charge trapping devices. The structural stability and the charge trapping characteristics of such stacks were investigated using Metal-Alumina-Hafnia-Oxide-Silicon (MAHOS) structure. The surface roughness of $HfO_2$ was stable up to 11 nm with the insertion of 0.2 nm thick $Al_2O_3$. The effect of the thickness of the HAH stack and the thickness of intermediate $Al_2O_3$ on charge trapping characteristics were investigated for MAHOS structure under various gate bias pulse with duration of 100 ms. The threshold voltage shift after programming and erase showed that the memory window was increased with increasing bias on gate. However, the programming window was independent of the thickness of HAH charge trapping layers. When the thickness of $Al_2O_3$insertion increased from 0.2 nm to 1 nm, the erase window was decreased without change in the programming window.