• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.461-463
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• 1999

In this paper, we have systematically investigated the variation of electrical characteristics with back-gate bias of n-channel SOI MOSFET\\`s. When positive bias is applied back-gate surface is inverted and back channel current is increased. When negative bias is applied back-gate surface is accumulated but it does not affect to the electrical characteristics.

• 한국전기전자재료학회논문지
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• 제21권2호
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1243-1246
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• 2009

A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.953-956
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• 2009

We have investigated the effect of light on amorphous silicon thin film transistors based photo-sensor applications. We have analyzed the instability caused by electrical gate bias stresses under the light illumination and the effect of photo-induced quasi-annealing on the instability. Threshold voltage ($V_{TH}$) under the negative gate bias stress with light illumination was more decreased than that under the negative gate bias stress without light illumination even though $V_{TH}$ caused by the light-induced stress without negative gate bias was shifted positively. These results are because the increase of carrier density in a channel region caused by the light illumination has the enhanced effect on the instability caused by negative gate bias stress. The prolonged light illumination led to the recovery of shifted VTH caused by negative gate bias stress under the light illumination due to the recombination of trapped hole charges.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1502-1504
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• 1996

The effects of electrical stress in hydrogen passivated and as-fabricated poly-Si TFT's are investigated. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which has been stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

• 한국전자파학회논문지
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• 제28권6호
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• pp.435-443
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• 2017

본 논문에서는 cascode 구조가 적용된 Class-E 스위칭 모드 CMOS 전력증폭기의 common-gate 트랜지스터 게이트 바이어스 효과에 대해 분석하였다. 게이트 바이어스 효과를 확인하기 위해서 전력증폭기의 DC 전력소모, 효율을 분석하였다. 분석 결과를 통해서 전력증폭기의 최고 효율을 보여주는 common-gate 트랜지스터의 게이트 바이어스가 일반적으로 사용하는 전력증폭기 전원 전압보다 낮음을 확인하였다. 트랜지스터의 게이트 바이어스가 계속 감소함에 따라 on-저항을 확인하여 커지고, 이에 따라 출력, 효율이 감소하는 것도 확인하였다. 이 두 가지 현상을 통해 게이트 바이어스가 스위칭 모드 전력증폭기에 미치는 영향을 분석하였다. 이 분석을 증명하기 위해서 $0.18{\mu}m$ RF CMOS 공정으로 1.9 GHz 스위칭 모드 전력증폭기를 설계하였다. 앞에서 설명한 것처럼 전력증폭기의 최대 효율은 전력증폭기의 인가 전압(3.3 V)보다 낮은 2.5 V에서 확인할 수 있었다. 이 때 최고 출력은 29.1 dBm, 최고 효율은 31.5 %이다. 측정 결과를 통해서 스위칭 모드 전력증폭기 common-gate 트랜지스터의 게이트 바이어스 효과를 실험적으로 확인하였다.

• 전기전자학회논문지
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• 제22권1호
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• pp.205-208
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• 2018

본 연구에서는 상시불통형 p-AlGaN-게이트 질화갈륨(GaN) 이종접합 트랜지스터의 신뢰성 평가를 위한 가속열화 시험 조건을 수립하기 위해 게이트 전압 열화 시험을 진행하였다. 상시불통형 트랜지스터의 동작 조건을 고려하여 기존 상시도통형 쇼트키-게이트 소자평가에 사용되는 게이트 역전압 시험과 더불어 순전압 시험을 수행하여 열화특성을 분석하였다. 기존 상시도통형 소자와 달리 상시불통형 소자에서는 게이트 역전압 시험에 의한 열화는 관찰되지 않은 반면, 게이트 순전압 시험에서 심한 열화가 관찰되었다. 상시불통형 질화갈륨 전력 반도체 소자의 신뢰성 평가에 게이트 순전압 열화 시험이 포함되어야 함을 제안한다.