• Journal of Power Electronics
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• v.19 no.4
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• pp.894-906
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• 2019

In this paper, a DC-DC converter is proposed based on the Cuk converter. The proposed converter has high efficiency and it can be used in multilevel DC-DC converters. A reduction of the inductors size in comparison to Cuk converter and a reduction in the inductors resistance negative effects on efficiency are the important points of the proposed converter. Its voltage ripple is reduced when compared to other converters. Its output voltage has a high quality and does not contain spikes. A theoretical analysis demonstrates the positive points of the proposed converter. The design and analysis of the converter are done in continues conduction mode (CCM). Experiments confirm the obtained theoretical equations. The proposed converter voltage gain is similar to that of a conventional Boost converter. As a result, they are compared. The comparison illustrates the advantages of the proposed converter and its higher quality. Furthermore, a prototype of the proposed converter and its combination with a 2x multiplier are built in the lab. Experimental results validate the analysis. In addition, they are in good agreements with each other.

• The Journal of Industrial Distribution & Business
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• v.14 no.5
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• pp.11-18
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• 2023

Purpose: The current research based on the comprehensive literature evaluation aims to gain insight into the factors contributing to an Oriental art gallery's success and the strategies used to advertise and sell these works effectively. Understanding and experience in Oriental art are essential for finding solutions to these issues. Research design, data and methodology: The current research conducted the following stages to conduct a thorough literature analysis on the issues that plague Oriental art gallery practitioners and the methods used to increase sales of this kind of art: Finding Valuable Resources and Subjects, Screening and Selection of Articles, Data Extraction and Analysis, Synthesis of Findings. Results: After reviewing the many aspects that affect the success of a gallery specializing in Oriental art, there were four key approaches that have emerged for boosting sales of this kind of artwork. Based on the findings, these approaches are grounded in four areas: consumer preferences; marketing methods; pricing strategies; and art investments. Conclusions: All in all, the current study finally indicates that practitioners should consider cultural background, age, gender, income, and level of education when developing marketing strategies and selecting artwork to exhibit. Target marketing is an effective method for attracting and retaining customers.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.673-684
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome this problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. Using the proposed gain control scheme, a low-voltage and high-speed CMOS VGA is designed. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than l.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$${\times}$360${\mu}{\textrm}{m}$.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.43-55
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• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.7
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• pp.3203-3210
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• 2013

Amid the importance of design is being emphasized as a new barometer for boosting enterprise competitiveness, high expectations are being placed on design consulting that evaluate design from a comprehensive perspective. SMEs, however, are not easy to gain access to design services compare to their counterparts - large companies. This will eventually cause them to ignore the importance of design, not to mention lack of financial resources for investing in design. With this regard, the paper analyzed the design status and design consulting performance of SMEs in industrial complex through the 2012 Design Innovation Project in Industrial Complex of Busan Design Center; also analyzed the effect of design consulting on improving competitiveness of SMEs as well as design awareness. As a result, the study found that a majority of companies do not invest in design or postponed investment, despite they are not satisfied with their design performance. However, 65.6 percent of SMEs that realized the importance of design after consulting have carried out design development, which brought about sales increase through their improved corporate images and product images. We believe design consulting played an important role for boosting awareness and competitiveness of SMEs. Eventually, we need to provide an intensified design analysis process that can facilitate SMEs. Design consulting support projects should offer practical design development programs through continuous follow-up, including interaction with state projects and design-specialized companies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.3
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• pp.361-366
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• 2012

This paper proposes a low power capacitor cross-coupled 5.2 GHz band low noise amplifier(LNA) using the current-reused topology with the TSMC 0.18 ${\mu}m$ CMOS process. The proposed 5.2 GHz band LNA uses a capacitor cross-coupled $g_m$-boosting method for reducing current flow of circuit and a current-reused topology to decrease total power dissipation. The parallel LC networks are used to reduce size of spiral inductors. The simulation results show high gain of 17.4 dB and noise figure(NF) of 2.7 dB for 5.2 GHz.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.229-237
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• 2011

In this paper, a 60 GHz LTCC SiP with low-power CMOS OOK modulator and demodulator is presented. The 60 GHz modulator is designed in a 90-nm CMOS process. The modulator uses a current reuse technique and only consumes 14.4-mW of DC power in the on-state. The measured data rate is up to 2 Gb/s. The 60 GHz OOK demodulator is designed in a 130nm CMOS process. The demodulator consists of a gain boosting detector and a baseband amplifier, and it recovers up to 5 Gb/s while consuming low DC power of 14.7 mW. The fabricated 60 GHz modulator and demodulator are fully integrated in an LTCC SiP with 1 by 2 patch antenna. With the LTCC SiP, 648 Mb/s wireless video transmission was successfully demonstrated at wireless distance of 20-cm.

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.