• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.655-661
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• 2006

Dielectric and piezoelectric properties of PMN-PZT ceramics with a high mechanical quality factor$(Q_m)$ and a low temperature sintering temperature were investigated as a function of PZN substitution in order to develop multilayer piezoelectric transformer for AC-DC converter. Multilayer piezoelectric transformers were subsequently manufactured using the PMN-PZN-PZT ceramic offering the optimal behavior and then the electrical performance were invetigated. At the sintering temperature of $940^{\circ}C$, density, electromechanical coupling factor$(k_p)$, mechanical qualify factor$(Q_m)$ and dielectric constant$(\varepsilon_r)$ of 8 mol% PZN substituted specimen were $7.73g/cm^3$, 0.524, 1573 and 1455, respectively. The PZN substitution caused a increase in the dielectric constant and the electromechnical coupling factor. The voltage step-up ratio of multilayer piezoelectric transformer showed the maximum value at near the resonant frequency of 76.55 kHz and increased according to the increase of load resistance. The multilayer piezoelectric transformer with the output impedance coincided with the load resistance showed the temperature increase of less than $20^{\circ}C$ at the output power of 10 W. Based on the results, the manufactured multilayer transformer using the low temperature sintered PMN-PZN-PZT ceramics can be stably driven for both step-up and down transformers.

• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.859-863
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• 2005

This paper describes the improvement of power control characteristics of ship's emergency lighting power supply(SELPS), by which electric power is controlled extensively, and power ON-OFF is controlled and system parameter monitored in remote distance by PC serial communication. Proposed system is composed of step-down converter(SDC), emergency power supply circuit(EPSC), half bridge(HB) inverter, fluorescent lamp(FL) starting circuit, microprocessor control and multi communication circuit. Experimental works confirm that relative system stops when over current is detected and speedy and stable emergency power is supplied when main power source cut-off, and controls input power up to 35[$\%$] by adjusting pulse frequency of the HB inverter, and ON-OFF control of multiple SELS, real time transmission and monitor of parameters as to voltage, current, and power values are performed appropriately by PC communication.

• Journal of the Korean Society of Marine Environment & Safety
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• v.17 no.1
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• pp.83-88
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• 2011

There are various environmental conditions under which ship may navigate over ocean or in harbor. Ship's torque and speed change frequently under the voyage conditions. In this case, harmonics is created in the electrical power systems. The major adverse impacts of voltage and current harmonics in the electrical power systems on generator, transformer, converter, inverter and propulsion motor lead to the increase of machine heating caused by iron and copper losses which are dependent on frequency. In this paper, an analysis of THD(total harmonic distortion) for currents and voltages in the propulsion equipment was carried out. The THD and torque ripple in the input currents of the propulsion motor have been confirmed by the simulation results.

• Journal of Magnetics
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• v.13 no.2
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• pp.37-42
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• 2008

In this paper, design parameters of high Q (> 50), high current inductor for on-chip power module were optimized by 4 Xs 3 Ys DOE (Design of Experiment). Coil spacing, coil thickness, ferrite thickness, and permeability were assigned to Xs, and inductance (L) and Q factor at 10 MHz, and resonance frequency ($f_r$) were determined Ys. Effects of each X on the Ys were demonstrated and explained using known inductor theory. Multiple response optimizations were accomplished by three derived regression equations on the Ys. As a result, L of 125 nH, Q factor of 197.5, and $f_r$ of 316.3 MHz were obtained with coil space of $127\;{\mu}m$, Cu thickness of $67.8\;{\mu}m$, ferrite thickness of $130.3\;{\mu}m$, and permeability 156.5. Loss tan ${\delta}=0$ was assumed for the estimation. Accordingly, Q factor of about 60 is expected at tan ${\delta}=0.02$.

• Journal of Sensor Science and Technology
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• v.5 no.4
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• pp.17-24
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• 1996

Planar multi-junction thermal converters were fabricated for precise measurements of the ac voltage and current by an ac-dc transfer method. A heater and a thermocouple array were fabricated onto a sandwiched membrane, $Si_{3}N_{4}$ (200 nm) / $SiO_{2}$ (400 nm) / $Si_{3}N_{4}$ (200 nm), a thickness of $0.8\;{\mu}m$ and a size of $2{\times}4\;mm^{2}$, which is supported by a surrounding frame. The NiCr heater is located at the center of the membrane vertically. Hot junctions of $48{\sim}156$ pairs of thermocouples (Cu-CuNi44) are located near or onto the heater, and cold junctions are located onto the silicon frame. Output of the thermal converters for 10 mA dc input was $76\;mV{\sim}382\;mV$ dependent on a model, and short term stability of the outputs was ${\pm}5{\sim}15\;ppm$/ 10 min with 5 mA dc input. Responsivity in air was in the range of $3.9{\sim}14.5V/W$. Responsivity of the model BF48 in air which has 48 thermocouples was 2 times or greater than that of 3 dimensional multi-junction thermal converter in vacuum which has 56 thermocouples. AC-DC transfer differences with an input of 10 mA or less were less than ${\pm}1\;ppm$ in the frequency range from 5 Hz to 2 kHz, and about $2{\sim}3\;ppm$ at 5 kHz and 10 kHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.