• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.379-380
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• 2012

A bidirectional full-bridge CLLC resonant converter using a digital control method is proposed for a LVDC power distribution system. This converter can operate under high power conversion efficiency since the CLLC resonant network has soft switching capability for primary switches and output rectifiers. In addition, the power conversion efficiency of any directions is exactly the same as each other because of the symmetric structure of the converter. Intelligent digital control methods are proposed to regulate output voltage under any power flow directions. A 5kW prototype converter was designed for a high-frequency galvanic isolation of 380V dc buses using a digital signal processor to verify the performance of the proposed topology and algorithms.

• Journal of the Korea Institute of Military Science and Technology
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• v.25 no.2
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• pp.144-150
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• 2022

The on-board processor of satellite synthetic aperture radar(SAR) generates transmission signal by digital signal processing, converts it into an analog signal. At this time, the transmission signal generated from the baseband requires the frequency modulation to convert it to the high-frequency band in order to improve the stability. General frequency modulation method using local oscillator(LO) causes IQ imbalance due to phase error/magnitude error and these error reduce performance of SAR. To generate transmission signal without phase/magnitude error, this paper suggests design method of the frequency modulation method using digital to analog converter(DAC) at on-board SAR. For design, this paper analyzes the characteristic of DAC mode and uses pre-compensation filter. To analyze the proposed method performance, performance index are compared with IQ imbalance signals. This method is suitable for on-board SAR using fast sampling DAC and has the advantage of being able to solve IQ imbalances.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.5
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• pp.336-342
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• 2017

Recently, there has been an increasing need for underwater communication systems to monitor ocean environments and prevent marine disasters, as well as to secure ocean resources. Most underwater communication systems adopted acoustic communication with a consideration of attenuation, absorption, and scattering in conductive sea water, and developed fully digital modems based on processors. In this study, a digital up converter (DUC) and a digital down converter (DDC) was developed for an underwater basestation based on underwater acoustic communication systems. Because one of the most important issues in underwater acoustic communication systems is low power consumption due to environmental problems, this study developed a specific hardware module for DUC and DDC. It supported four links of underwater acoustic communication systems and converted the sampling rate and frequency. The systemwas designed and verified using Verilog-HDL in ModelSim environment with the test data generated from baseband layer parts for an underwater base station.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.126-137
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. And we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

• Journal of Power Electronics
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• v.10 no.5
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• pp.451-460
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• 2010

This paper presents a new kind of digital control metal halide lamp electronic ballast. A zero-voltage-switch quasi-square-wave (ZVS-QSW) dual Buck converter is adopted here. In this paper, a digital control method is proposed to achieve ZVS for the converter. This ZVS can be realized during the whole working condition. Single-cycle-peak-current control is proposed to solve the problem of excessive inductor current during a low-frequency reversal transient. Power loop control is also realized and its consistency for different lamps is good. An AVR special microcontroller for a HID ballast is used to raise the control performance, and the low-frequency square-wave control method is adopted to avoid acoustic resonance. A 70W prototype was built in the laboratory. Experimental results show that the electronic ballast works reliably. Furthermore, the efficiency of the ballast can be higher than 92%.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1206-1208
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• 1993

This paper is to study and realize a measuring device for complex dielectric constants. The device is consisted in order of interface unit, external RAM, programmable counter, D/A converter, measuring circuit, Sample & Hold circuit, A/D converter and related control circuits. Various excitation waves are digitalized and sent to the 4096 static RAM by personal computer. These data saved in the RAM are converted to analog excitation waves through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM according to clock pulses. Such generated waves are applied to dielectrics under test and their responses are sampled and converted to digital data through A/D converter. The computer takes the digital data and calculates finally the complex dielectric constants. The frequencies for Measurement ranges from 0.04 Hz to 10 kHz.

• The Journal of the Acoustical Society of Korea
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• v.9 no.3
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• pp.48-55
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• 1990

We analyze the effect of second-order sampling on estimating the mean frequency of the Doppler signal. In order to reduce the sampling frequency of analogue-to-digital converter, it is possible to obtain the Doppler signal by sampling the radio frequency echo signal with the low frequence of $4f_0$/5 or $4f_0$/9 instead of $4f_0$, where $f_0$ is the center frequency of the transmitted signal. The computer simulation and experiments show that if the narrowband signal is transmitted as is usual in the Doppler system, the error of the mean frequency estimates due to the low sampling frequency is negligible.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.442-446
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• 1998

With the advent of the high-speed microprocessor and DSP, the possibility of executing a control strategy in digital domain has become a reality. By the use of the DSP and microprocessor controller, many high power converters such as especially inverter and motor drive system may be enhanced resulting in the improved robustness to EMI, the ability to communicate the operating conditions and the ease of adjusting the control parameters. But, the digital controller using DSP or microprocessor is not applied in the high frequency switching power supplies, especially full bridge dc/dc converter. So, this paper presents the method and realization of designing a digital-to-phase shift PWM circuit for full digital controlled phase-shifted full bridge dc/dc converter with zero voltage switching. The operating principles, simulation and experimental results will be presented.