• KIEE International Transactions on Electrophysics and Applications
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• 제3C권6호
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• pp.220-223
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• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• Journal of Power Electronics
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• 제4권3호
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• pp.152-160
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• 2004

This paper presents analysis, modeling, and design of a low-harmonic, isolated, active-clamped SEPIC for future avionics applications. Simpler converter dynamics, high switching frequency, zero voltage-Transition-PWM switching, and a single-layer transformer construction result. This paper describes complete design of a digital controller for a high-frequency switching power supply. Guidelines for the minimum required resolution of the analog-to-digital converter, the pulse-width modulator, and the fixed-point computational unit is derived. A design example based on a SEPIC converter operating at the high switching frequency is presented. The controller design is based on direct digital design approach and standard root-locus techniques.

• 한국컴퓨터정보학회논문지
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• 제7권4호
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• pp.115-120
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• 2002

본 논문은 Field Programmable Gate Array (FPGA)와 디지털 신호처리 소자를 이용한 IS-95 CDMA신호 처리기 FPGA와 고속의 ADC/DAC를 이용한 기저대역과 중간주파수(IF)의 디지털 변환기 그리고 주파수 상·하향 변환기를 구현하였다. IS-95 CDMA 채널 처리기는 짧은 PN 코드 발생기와 왈쉬 코드 발생기로 파일롯 채널의 신호를 발생시킨다. 디지털 IF는 FPGA, 디지털 송·수신 신호처리 소자와 고속의 ADC/DAC로 구성하였다. 주파수 상·하향 변환기는 필터, 믹서, 디지털 감쇠기와 PLL로 구성되어 중간주파수(IF)와 RF 주파수를 변환하였다. 이 구현된 시스템은 IS-95 CDMA 기지국 장비 등에 장착할 수 있다.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

• 한국산학기술학회논문지
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• 제15권5호
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• pp.3079-3085
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• 2014

본 논문에서는 수동소자를 이용한 필터 설계기술을 기반으로 하고 디지털 계단형 감쇠기를 이용하여 전력레벨 조절이 가능한 주파수 상향 변환기를 설계 및 제작하였다. 제작한 주파수 변환기는 저전력 및 저가의 제작비용을 실현하였으며 전력레벨의 조절이 가능하여 광범위한 영역에서 사용이 가능하다. 실험 결과, 중심 주파수 1, 200MHz에서 160MHz의 대역을 확보하였으며 이득은 평균 0.75dB임을 확인하였다. 또한, 디지털 감쇠기를 통해 전력레벨을 10~-21.5dBm까지 조절이 가능함을 확인하였다.

• 전기전자학회논문지
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• 제25권2호
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• pp.302-308
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• 2021

본 논문에서는 영상 처리용 12-비트의 10-MS/s 파이프라인 아날로그-디지털 변환기(ADC: analog-to-digital converter)가 제안된다. 제안된 ADC는 샘플-홀드 증폭기, 3개의 stage, 3-비트 플래시 ADC, 그리고 digital error corrector로 구성된다. 각 stage는 4-비트 flash ADC와 multiplying digital-to-analog ADC로 구성된다. 고해상도의 ADC를 위해 제안된 샘플-홀드 증폭기는 gain boosting을 이용하여 전압 이득을 증가시킨다. 제안된 파이프라인 ADC는 1.8V 공급전압을 사용하는 180nm CMOS 공정에서 설계되었고 차동 1V 전압을 가지는 1MHz 사인파 아날로그 입력신호에 대해 10.52-비트의 유효 비트를 가진다. 또한, 약 5MHz의 나이퀴스트 사인파 입력에 대해 측정된 유효비트는 10.12 비트이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.233-236
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• 2000

A new time-to-digital converter is designed and the converter is based on a voltage-to-frequency converter and a counter. The converter output is obtained without delay time and the resolution improves with increasing input time interval because the output of voltage-to-frequency converter increases linearly. In the designed circuit the input time intervals range is from 100nsec to 3${\mu}$ sec.