• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.6
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• pp.220-223
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• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• Journal of Power Electronics
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• v.4 no.3
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• pp.152-160
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• 2004

This paper presents analysis, modeling, and design of a low-harmonic, isolated, active-clamped SEPIC for future avionics applications. Simpler converter dynamics, high switching frequency, zero voltage-Transition-PWM switching, and a single-layer transformer construction result. This paper describes complete design of a digital controller for a high-frequency switching power supply. Guidelines for the minimum required resolution of the analog-to-digital converter, the pulse-width modulator, and the fixed-point computational unit is derived. A design example based on a SEPIC converter operating at the high switching frequency is presented. The controller design is based on direct digital design approach and standard root-locus techniques.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3079-3085
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• 2014

This paper suggests a power level controllable frequency up-converter which is designed and fabricated using both the filtering technology consisted with only passive devices and a multi-level digital attenuator. The suggested frequency up-converter simultaneously realizes the low power consumption and the low cost model. Because of the possibility for controlling power levels, it is possible to use the suggested frequency up-converter for wide spectral range. According to the experimental results, the average gain value of 0.75dB is obtained for the bandwidth of 160MHz at the center frequency of 1,200MHz. Especially, it is confirmed that the power level can be controlled from 10 to -21.5dBm through the digital attenuator.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.233-236
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• 2000

A new time-to-digital converter is designed and the converter is based on a voltage-to-frequency converter and a counter. The converter output is obtained without delay time and the resolution improves with increasing input time interval because the output of voltage-to-frequency converter increases linearly. In the designed circuit the input time intervals range is from 100nsec to 3${\mu}$ sec.