• 전자공학회논문지SC
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• 제44권1호
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• pp.74-84
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• 2007

본 논문에서는 기존의 DLL 지연 시간 잠금 범위를 확장하기 위해 새로운 이중 루프 DLL을 제안하였다. 제안한 DLL은 Coarse_loop와 Fine_loop를 포함하고 있으며, 와부 클럭과 2개의 내부 클럭 사이의 초기 시간차를 비교하여 하나의 루프를 선택하여 동작하게 된다. 2개의 내부 클럭은 VCDL의 중간 출력 클럭과 최종 출력 클럭이며 두 클럭의 위상차는 $180^{\circ}$이다. 제안한 DLL은 일반적인 잠금 범위 밖에 있을 경우 Coarse_loop를 선택하여 잠금 범위 안으로 이전 시킨 후 Fine_loop에 의하여 잠금 상태가 일어난다. 따라서 제안한 DLL은 harmonic lock이 일어나지 않는 한 항상 안정적으로 잠금 과정이 일어날 수 있게 된다. 제안한 DLL이 사용하는 VCDL은 두 개의 제어 전압을 받아 지연 시간을 조절함으로 일반적인 다 적층 currentstarved 형태의 인버터 대신에 TG 트랜지스터를 이용하는 인버터를 사용하여 지연 셀을 구성하였다. 새로운 VCDL은 종래의 VCDL에 비하여 지연시간 범위가 더욱 확장되었으며, 따라서 제안한 DLL의 잠금 범위는 기존의 DLL의 잠금 범위보다 2배 이상 확장되었다. 본 논문에서 제안한 DLL 회로는 0.18um, 1.8V TSMC CMOS 라이브러리를 기본으로 하여 설계, 시뮬레이션 및 검증하였으며 동작 주파수 범위가 100MHz${\sim}$1GHz이다. 또한, 1GHz에서 제안한 DLL의 잠금 상태에서의 최대 위상 오차는 11.2ps로 높은 해상도를 가졌으며, 이때 소비 전력은 11.5mW로 측정되었다.

• ETRI Journal
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• 제21권3호
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• pp.1-5
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• 1999

A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제55권1호
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• pp.39-46
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• 2006

PLL is a key item of power converter for power quality compensation and power flow control. This paper proposes a novel 3-phase PLL that is composed of ALC and PI controller. The operational principle was investigated through theoretical approach, and the performance was verified through computer simulations with MATLAB and experimental works with TMS320VC33 DSP board. The proposed 3-phase PLL shows accurate performance under the voltage disturbances such as sag, harmonics. phase-angle jump, and frequency change.

• Journal of Power Electronics
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• 제15권4호
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• pp.1085-1092
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• 2015

In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the n^th-order harmonics cause n+1^th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.79-82
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• 2000

This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input.

• 전자공학회논문지
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• 제51권1호
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• pp.90-96
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• 2014

본 논문은 광대역 특성의 뱅뱅 디지털 위상 동기 루프를 설계함에 있어 최적의 루프 이득 선정을 통한 실용적인 선형화 설계 기법을 제안한다. 기존의 이론적 파라미터 설계 기법을 광대역 클럭 발생기 회로에 적용함에 있어 한계점을 설명하고 실제 구현된 뱅뱅 디지털 위상 동기 루프 설계에 대해서 살펴보았다. 본 논문에서는 정수 어레이와 디더 이득은 크게 하되 비례 이득을 작게 설정하여 뱅뱅 디지털 위상 동기 루프의 리미티드 사이클 노이즈를 제거하였다. 제안된 설계 기법을 적용한 뱅뱅 디지털 위상 동기 루프는 기존의 구조에 비교하여 초소형, 저전력, 선형 특성 및 루프 대역폭 조절이 가능한 장점을 보이며, 성능의 우수성을 시뮬레이션을 통하여 검증하였다.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.717-718
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• 2013

CMOS로 구성된 전압-제어 발진기의 채널 폭과 길이가 변화하면, 입력 전압에 따른 출력 주파수가 변화할 것이다. 본 논문에서는 FLL(Frequency Locked Loop) 회로의 구성 요소로 사용되는 전압-제어 발진기의 채널 폭 변화에 따른 전기적인 특성 변화를 시뮬레이션을 통하여 살펴보고자 한다. 그리고 변화하는 채널 폭에 따른 전압-제어 발진기의 신뢰성 특성을 향상하기 위한 방안을 살펴보고자 한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.47-48
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• 2013

In order to evaluate the response of the grid-connected systems, Phase lock technology is widely used in power electronic devices to obtain the phase angle, amplitude, and frequency of the grid voltage because phase locked loop (PLL) algorithms are very important for grid synchronization and monitoring in the grid connected power electronic devices. This paper presents a performance evaluation in tracking grid angular frequency through single phase synchronization techniques which are an enhanced PLL (EPLL), second-order generalized integrator-PLL (SOGI-PLL), and second-order generalized integrator-frequency locked loop (SOGI-FLL). These techniques are properly analyzed through several steps to get the best technique which can track the frequency accurately and smoothly.

• Journal of Power Electronics
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• 제16권1호
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• pp.18-26
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• 2016

This paper proposes a compensation algorithm for reducing a specific ripple component on synchronous reference frame phase locked loop (SRF-PLL) in grid-tied single-phase inverters. In general, SRF-PLL, which is based on all-pass filter to generate virtual voltage, is widely used to estimate the grid phase angle in a single-phase system. In reality, the estimated grid phase angle might be distorted because the phase difference between actual and virtual voltages is not 90 degrees. That is, the phase error is caused by the difference between cut-off frequency of all-pass filter and grid frequency under grid frequency variation. Therefore, the effects on phase angle and output current attributed to the phase error are mathematically analyzed in this paper. In addition, the proportional resonant (PR) controller is adapted to reduce the effects of phase error. The validity of the proposed algorithm is verified through several simulations and experiments.