• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

• Tribology and Lubricants
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• 제19권6호
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• pp.342-348
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• 2003

The purpose of the paper is to investigate the noise characteristics of cylindrical roller bearings. For the sake of simplicity, it is assumed that the cylindrical roller bearing is infinitely long, and there is no outside force acting on the bearing. The effects of radial clearance of the bearing, viscosity of the lubricant and number of the roller on the noise of the bearing are also examined. Results show that the fundamental frequency of the bearing noise corresponds to the multiplication of number of the roller and whirling frequency of the roller center or the retainer. The acoustical frequency spectra of the roller bearing are pure tone spectra, containing the fundamental frequency of the bearing and its super­harmonics. The low viscosity of the lubricant, high radial clearance of the bearing, and low number of the roller decrease the bearing noise. The results and discussions of the present paper could aid in the low­noise design of the cylindrical roller bearing.

• 한국전자파학회논문지
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• 제7권4호
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• pp.336-345
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• 1996

SO(synchronous oscillator)는 외부 인가 신호가 없을시에도 발진하는 자려발진기이며 펄스파, 정현파, 비주기적인파 등 어떠한 외부 신호에도 즉시 동기 발진하고, 출력은 일정한 동조대역폭으로 동기한다. 이러한 특성은 SO가 분주 및 체배기로 사용 가능함을 의미하며, 코히런트 디지혈 통신의 동기 문제점을 해결할 수 있을 것이며, 또 이와 같은 특성을 이용하여 DS/SS 동기적용을 위한 SO의 동기 특성을 실험을 통하여 입증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• 한국정보통신학회논문지
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• 제21권6호
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• pp.1083-1091
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• 2017

NIST 표준에 정의된 소수체(prime field) GF(p) 상의 224-비트 타원곡선을 지원하는 타원곡선 암호 프로세서를 설계하였다. 타원곡선 암호의 핵심 연산인 스칼라 점 곱셈을 수정형 Montgomery ladder 알고리듬을 이용하여 구현하였다. 점 덧셈과 점 두배 연산은 투영(projective) 좌표계를 이용하여 연산량이 많은 나눗셈 연산을 제거하였으며, 소수체 상의 덧셈, 뺄셈, 곱셈, 제곱 연산만으로 구현하였다. 스칼라 점 곱셈의 최종 결과값은 다시 아핀(affine) 좌표계로 변환되어 출력하며, 이때 사용되는 역원 연산은 Fermat's little theorem을 이용하여 구현하였다. 설계된 ECC 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였다. $0.18{\mu}m$공정의 CMOS 셀 라이브러리로 합성한 결과 10 MHz의 동작 주파수에서 2.7-Kbit RAM과 27,739 GE로 구현되었고, 최대 71 MHz의 동작 주파수를 갖는다. 스칼라 점 곱셈에 1,326,985 클록 사이클이 소요되며, 최대 동작 주파수에서 18.7 msec의 시간이 소요된다.

• Journal of Plant Biotechnology
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• 제5권4호
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• pp.225-231
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• 2003

The hormonal requirement suiting micropropagation of Morus alba during any season throughout the year was studied. Sprouting frequency from axillary buds of M. alba was greatly influenced by the time of explant collection, the highest value was achieved when nodal explants were collected at the end of bud dormancy period (late in March) and cultured on Murashige and Skoog (MS) medium supplemented with low concentration (0.5 mg/L) of BAP, kinetin or IBA (85-68%). In addition, they showed higher axillary bud sprouting on growth-regulators-free medium (49%) than others collected in autumn or winter and cultured on medium supplemented with various growth regulators (47-48%). Regardless of that period, young explants with greenish buds collected in summer exhibiting high sprouting frequency (66%) on MS medium supplemented with 0.5 mg/L kinetin and 0.5 mg/L GA3. Shoot multiplication via adventitious bud formation was achieved when the nodal explants were cultured on MS medium supplemented with 2 mg/L BAP and 0.2 mg/L IBA. Further multiplication via nodal explants of in vitro grown shoots was obtained on MS medium supplemented with 0.5 mglL BAP and 0.5 mg/L GA3. While half strength MS medium supplemented with low concentration (0.5 mg/L) of IBA, IAA or 2,4-D stimulated adventitious root formation, IBA was the best. After transfer the plantlets to the soil, acclimatization for three weeks was essential prerequisite for survival in high frequency (92%). Peroxidase activity is related to break of bud dormancy where maximum enzyme activity was detected when the lateral buds were induced to commence growth under field condition (early in spring) or in vitro.

• 전기전자학회논문지
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• 제22권4호
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• pp.1158-1162
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• 2018

안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수 증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ~ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는 MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.

• 전기전자학회논문지
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• 제12권4호
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• pp.234-238
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• 2008

We demonstrate a simple method to generate a stable 40 GHz pulse train at 1550 nm by spectral filtering of a 10 GHz mode.locked pulse source using a fiber Fabry-Perot interferometer (FFPI). A high finesse FFPI with a 40 GHz free spectral range blocks successfully unwanted spectral components of a 10 GHz pulse source and passes only 40 GHz spaced spectral lines ensuring pulse repetition-frequency quadruplication of the input pulses.

• Journal of information and communication convergence engineering
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• 제3권3호
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• ETRI Journal
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• 제32권4호
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• pp.520-529
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• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.