• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

• Tribology and Lubricants
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• v.19 no.6
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• pp.342-348
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• 2003

The purpose of the paper is to investigate the noise characteristics of cylindrical roller bearings. For the sake of simplicity, it is assumed that the cylindrical roller bearing is infinitely long, and there is no outside force acting on the bearing. The effects of radial clearance of the bearing, viscosity of the lubricant and number of the roller on the noise of the bearing are also examined. Results show that the fundamental frequency of the bearing noise corresponds to the multiplication of number of the roller and whirling frequency of the roller center or the retainer. The acoustical frequency spectra of the roller bearing are pure tone spectra, containing the fundamental frequency of the bearing and its super­harmonics. The low viscosity of the lubricant, high radial clearance of the bearing, and low number of the roller decrease the bearing noise. The results and discussions of the present paper could aid in the low­noise design of the cylindrical roller bearing.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.4
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• pp.336-345
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• 1996

The S.O(synchronous osillator) oscillates at its natural frequency without the externa applied signal. But if the external signal is applied, the S.O starts to track the external frequency which can be sinusoidal, pulsed or some other waveform. Thus, the output is synchronized with the wide range of tracking bandwidth to the external frequency. Specifically, the S.O also posses frequency division and multiplication capability. All of these indicate that the S.O can overcome the difficulties of syschronization in coherent digital communication systems. This papers proposed application of DS/SS communication with study on the synchronous properties of S.O.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1083-1091
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• 2017

This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat's little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.

• Journal of Plant Biotechnology
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• v.5 no.4
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• pp.225-231
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• 2003

The hormonal requirement suiting micropropagation of Morus alba during any season throughout the year was studied. Sprouting frequency from axillary buds of M. alba was greatly influenced by the time of explant collection, the highest value was achieved when nodal explants were collected at the end of bud dormancy period (late in March) and cultured on Murashige and Skoog (MS) medium supplemented with low concentration (0.5 mg/L) of BAP, kinetin or IBA (85-68%). In addition, they showed higher axillary bud sprouting on growth-regulators-free medium (49%) than others collected in autumn or winter and cultured on medium supplemented with various growth regulators (47-48%). Regardless of that period, young explants with greenish buds collected in summer exhibiting high sprouting frequency (66%) on MS medium supplemented with 0.5 mg/L kinetin and 0.5 mg/L GA3. Shoot multiplication via adventitious bud formation was achieved when the nodal explants were cultured on MS medium supplemented with 2 mg/L BAP and 0.2 mg/L IBA. Further multiplication via nodal explants of in vitro grown shoots was obtained on MS medium supplemented with 0.5 mglL BAP and 0.5 mg/L GA3. While half strength MS medium supplemented with low concentration (0.5 mg/L) of IBA, IAA or 2,4-D stimulated adventitious root formation, IBA was the best. After transfer the plantlets to the soil, acclimatization for three weeks was essential prerequisite for survival in high frequency (92%). Peroxidase activity is related to break of bud dormancy where maximum enzyme activity was detected when the lateral buds were induced to commence growth under field condition (early in spring) or in vitro.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of IKEEE
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• v.12 no.4
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• pp.234-238
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• 2008

We demonstrate a simple method to generate a stable 40 GHz pulse train at 1550 nm by spectral filtering of a 10 GHz mode.locked pulse source using a fiber Fabry-Perot interferometer (FFPI). A high finesse FFPI with a 40 GHz free spectral range blocks successfully unwanted spectral components of a 10 GHz pulse source and passes only 40 GHz spaced spectral lines ensuring pulse repetition-frequency quadruplication of the input pulses.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• ETRI Journal
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• v.32 no.4
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• pp.520-529
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• 2010

In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation frequency network are described in detail. The LDO works with a supply voltage as low as 1.2 V and provides a maximum load current of 50 mA with a drop-out voltage of 200 mV: the total integrated compensation capacitance is about 40 pF. Measurement results as well as comparison with other SoC LDOs demonstrate the advantage of the proposed topology.