• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.570-576
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• 2004

In this paper, we design the IFFT/FFT (Inverse fast Fourier Transform/Fast Fourier Transform) modules for IEEE 802.11a-1999, which is a standard of the High-speed Wireless LAN using the OFDM (Orthogonal Frequency Division Multiplexing). The designed IFFT/FFT is the 64-point FFT to be compatible with IEEE 802.11a and the pipelined architecture which needs neither serial-to-parallel nor parallel-to-serial converter. We compare four types of IFFT/FFT modules for the hardware complexity and operation : R22SDF (Radix-2 Single-path Delay feedback), the R2SDF (Radix-2 Single-path Delay feedback), R2SDF (Radix-4 Single-path Delay Feedback), and R4SDC (Radix-4 Single-path Delay Commutator). In order to minimize the error, we design the IFFT/FFT module to operate with additional decimal parts after butterfly operation. In case of the R22SDF, the IFFT/FFT module has 44,747 gate counts excluding RAMs and the minimized error rate as compared with other types. And we know that the R22SDF has a small hardware structure as compared with other types.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.2
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• pp.168-174
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• 2016

In this paper, current control using PI controller in the synchronous reference frame is analyzed through the relationship among bandwidth, resonance frequency, and sampling frequency in the grid-connected inverter with LCL filter. Stability is investigated by using bode plot in frequency domain and root locus in discrete domain. The feedback variable is the grid current, which is regulated by the PI controller in the synchronous reference frame. System delay is modeled as 1.5Ts, which contains computational and PWM modulator delay. Two resonance frequencies are given at 815 Hz and 3.16 kHz from LCL filter parameters. Sufficient phase and gain margins can be obtained to guarantee stable current control, in case that resonance frequency is above one-sixth of the sampling frequency. Unstable current control is performed when resonance frequency is below one-sixth of the sampling frequency. Analysis results of stability from frequency response and discrete response is the same regardless of resonance frequency. Finally, stability of current control based on theoretical analysis is clearly verified through simulation and experiment in grid-connected inverters with LCL filter.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.5
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• pp.131-138
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• 2008

The channel parameters such as RMS delay spread and Doppler frequency have an effect on performance of system. This paper investigates the effect between the Inter-Code Interference (ICI) and the frequency diversity gain in the multi-rate MC-CDMA system. The multi-rate MC-CDMA system has achieved the more variable data rate than the MC-CDMA and moreover it has the better performance than the OFDMA system, because it has achieved the frquency diversity gain. However, the frequency diversity gain and ICI have a trade-off relationship by using the spreading code. Therefore, we have improved the system performance by efficient choice of system parameters. In order to evaluate the effectiveness of the frequency diversify gain and the ICI effect, we perform simulations by altering the Doppler frequency and RMS delay spread.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.181-184
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• 2017

This study analyzes the turn-on and turn-off transients of a metal-oxide-semiconductor field-effect transistor (MOSFET) with high-switching frequency systems. In these systems, the voltage distortion becomes serious at the output terminal of a Vienna rectifier by the turn-off delay of the MOSFET. The current has low-order harmonics through this voltage distortion. This paper describes the transient of the turn-off that causes the voltage distortion. The algorithm for reducing the sixth harmonic using a proportional-resonance controller is proposed to improve the current distortion without complex calculation for compensation. The reduction of the current distortion by high-switching frequency is verified by experiment with the 2.5-kW prototype Vienna rectifier.

• Nuclear Engineering and Technology
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• v.56 no.4
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• pp.1454-1459
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• 2024

Researchers have applied theoretical and CFD models for years to analyze the fluidelastic instability (FEI) of tube arrays in steam generators and other heat exchangers. The accuracy of each approach has typically been evaluated using the discrepancy between the experimental critical flow velocity and the predicted value. In the best cases, the predicted critical flow velocity was within an order of magnitude comparable to the measured one. This paper revisits the quasi-steady approach for damping controlled FEI in a normal triangular array with a pitch ratio of P/d = 1.375. The method addresses the fluidelastic frequency at the stability threshold as an input parameter for the approach. The excellent agreement between the estimated stability thresholds and the equivalent experimental results suggests that the fluidelastic frequency must be included in the quasi-steady analysis, which requires minimal computing time and experimental data. In addition, the model allows a simple time delay analysis regarding flow convective and viscous effects.

• Journal of Advanced Navigation Technology
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• v.16 no.4
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• pp.602-610
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• 2012

Ionospheric delay error, one of main error sources in GPS signal, varies with signal frequency. Dual-frequency user uses L1, L2 frequency pseudorange to estimate the ionospheric delay, and there are errors caused by pseudorange measurement noise. So, filter is usually used to smooth the measurement. Weighted hatch filter can estimate optimal smoothed pseudorange measurement. But measurement noise model is needed to use this filter. In this paper, measurement noise modeling is conducted for NDGPS reference station. Using noise modeling result, weighted hatch filter estimate smoothed pseudorange measurement and ionospheric delay. Standard deviation of ionospheric dealy error drops to one-twenty fifth of non-filtered result.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5860-5876
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• 2018

A single snapshot data can only provide limited amount of information so that the rank of covariance matrix is not full, which is not adopted to complete the parameter estimation directly using the traditional super-resolution method. Aiming at solving the problem, a joint time delay and angle estimation using matrix pencil method based on information reconstruction vector for orthogonal frequency division multiplexing (OFDM) signal is proposed. Firstly, according to the channel frequency response vector of each array element, the algorithm reconstructs the vector data with delay and angle parameter information from both frequency and space dimensions. Then the enhanced data matrix for the extended array element is constructed, and the parameter vector of time delay and angle is estimated by the two-dimensional matrix pencil (2D MP) algorithm. Finally, the joint estimation of two-dimensional parameters is accomplished by the parameter pairing. The algorithm does not need a pseudo-spectral peak search, and the location of the target can be determined only by a single receiver, which can reduce the overhead of the positioning system. The theoretical analysis and simulation results show that the estimation accuracy of the proposed method in a single snapshot and low signal-to-noise ratio environment is much higher than that of Root Multiple Signal Classification algorithm (Root-MUSIC), and this method also achieves the higher estimation performance and efficiency with lower complexity cost compared to the one-dimensional matrix pencil algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1133-1138
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• 2007

DLLs(Delay Locked Loops) have widely been used in many systems in order to achieve the clock synchronization. A SMD (Synchronous Mirror Delay) structure is used both for skew reduction and for DCC (Duty Cycle Correction). In this paper, a SMD based DLL with DCC using Reduced Delay Lines is proposed in order to reduce the clock skew and correct the duty cycle. The merged structure allows the forward delay array to be shared between the DLL and the DCC, and yields a 25% saving in the number of the required delay cells. The designed chip was fabricated using a $0.25{\mu}m$ 1-poly, 4-metal CMOS process. Measurement results showed the 3% duty cycle error when the input signal ranges from 80% to 20% and the clock frequency ranges from 400MHz to 600MHz. The locking operation needs 3 clock and duty correction requires only 5 clock cycles as feature with SMD structure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.394-397
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• 2003

Since the speed of operation in the system has been increasing rapidly, chips should have been synchronized. Then, synchronized circuits such as PLL (Phase Locked Loop), DLL (Delay Locked Loop) are used. VCO (Voltage Controled Oscillator) generated a frequency in the PLL has disadvantage such as jitter accumulation. On the other hands, VCDL (Voltage Controled Delay Line) used at DLL has an advantage which has no jitter accumulation. In this paper, a new and improved VCDL structure is suggested.