• Title/Summary/Keyword: fractional-N

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Biodegradation of diesel oil and n-alkanes (C18, C20, and C22) by a novel strain Acinetobacter sp. K-6 in unsaturated soil

  • Chaudhary, Dhiraj Kumar;Bajagain, Rishikesh;Jeong, Seung-Woo;Kim, Jaisoo
    • Environmental Engineering Research
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    • v.25 no.3
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    • pp.290-298
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    • 2020
  • A large residual fraction of aliphatic components of diesel prevails in soil, which has adverse effects on the environment. This study identified the most bio-recalcitrant aliphatic residual fraction of diesel through total petroleum-hydrocarbon fractional analysis. For this, the strain Acinetobacter sp. K-6 was isolated, identified, and characterized and investigated its ability to degrade diesel and n-alkanes (C18, C20, and C22). The removal efficiency was analysed after treatment with bacteria and nutrients in various soil microcosms. The fractional analysis of diesel degradation after treatment with the bacterial strains identified C18-C22 hydrocarbons as the most bio-recalcitrant aliphatic fraction of diesel oil. Acinetobacter sp. K-6 degraded 59.2% of diesel oil and 56.4% of C18-C22 hydrocarbons in the contaminated soil. The degradation efficiency was further improved using a combinatorial approach of biostimulation and bioaugmentation, which resulted in 76.7% and 73.7% higher degradation of diesel oil and C18-C22 hydrocarbons, respectively. The findings of this study suggest that the removal of mid-length, non-volatile hydrocarbons is affected by the population of bio-degraders and the nutrients used in the process of remediation. A combinatorial approach, including biostimulation and bioaugmentation, could be used to effectively remove large quantities of aliphatic hydrocarbons persisting for a longer period in the soil.

Design of Fractional-N Digital PLL for IoT Application (IoT 어플리케이션을 위한 분수분주형 디지털 위상고정루프 설계)

  • Kim, Shinwoong
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.800-804
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    • 2019
  • This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

An analysis of Multi-mode LDPC Decoder Performance for IEEE 802.11n WLAN (IEEE 802.11n WLAN용 Multi-mode LDPC 복호기의 성능 분석)

  • Park, Hae-Won;Na, Young-Heon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.80-83
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    • 2010
  • This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

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An analysis of Optimal Design Conditions of Multi-mode LDPC Decoder for IEEE 802.11n WLAN System (IEEE 802.11n WLAN용 다중모드 LPDC 복호기의 최적 설계조건 분석)

  • Park, Hae-Won;Na, Young-Heon;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.2
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    • pp.432-438
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    • 2011
  • This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

Fractional Anisotropy of Diffusion Tensor Imaging as a Predict Factor in Patient with Acute Cerebral Infarction (급성 뇌경색 환자에서 예후 추측인자로서의 확산텐서영상 비등방도)

  • Kim, Sung-Gil;Eun, Sung-Jong
    • Journal of the Korean Society of Radiology
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    • v.4 no.3
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    • pp.13-18
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    • 2010
  • Purpose : Diffusion tensor imaging(DTI) allows the visualization of fiber tract damage in patients with cerebral infarction. The purpose of this study is to evaluate the correlation between degree of NIH stoke scale and fractional anisotropy (FA) in patient with cerebral infarction. Material and Methods : 16 patients aged 36~77 years(male : 11, female : 5, mean age : 61y), diagnosed cerebral infarction by diffusion weighted imaging(DWI), underwent 24 directional diffusion tensor imaging(DTI). Patients had the DTI taken within 3days of stroke onset. Comparison of DWI, FA value on DTI were measured infarcted area and counter part of specific region of interest (ROI). And evaluation of differences between clinically improved patient group (n=9) and unimproved patient group (n=7) until 2 week follow up after development of cerebral infarction. Clinical status was scaled by NIH stroke scale. Results : Quantitative measurements of FA confirmed statistically the significant diffusion changes in the infarct compared with the matched-counter part region. In DWI, the infarcted area shows high signal intensity, however FA value on DTI was lower than normal brain parenchyma. The FA value of clinically improved patient by NIH stroke scale was 0.49, and the value of contralateral normal brain parenchyma was 0.41. On the contrary, FA value of infarcted area shows about 15% lower than normal brain parenchyma. But, the FA value of unimproved patient by NIH stroke scale represents a half those of contralateral normal brain parenchyma (0.28 on infarcted area vs. 0.56 on normal brain parenchyma). So, the FA value of unimproved patient group was considerably less than those of improved. Conclusion : It is concluded that the unimproved patient group after cerebral infarction showed much less FA value than that of normal brain parenchyma. The FA value of DTI may be one of the useful parameter to predict outcome of cerebral infarction patients.

Photoaddition Reactions of trans-1,2-Bispyrazylethylene to Tetramethylethylene (테트라메틸에틸렌에 대한 트란스-1,2-비스피라질에틸렌의 광첨가반응)

  • Sang Chul Shim;Jin Ho Cho
    • Journal of the Korean Chemical Society
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    • v.23 no.5
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    • pp.325-328
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    • 1979
  • trans-1,2-Bispyrazylethylene (BPE) undergoes photoaddition reaction to tetramthylethylene (TME) which appears to involve radical intermediates under conditions where the corresponding hydrocarbons are unreactive. This photoaddition reaction involves abstraction of an allylic hydrogen atom of TME by $^1(n,\;{\pi}^*)$ states of BPE having radical character. The major photoadduct is isolated by column chromatography and fractional vacuum sublimation and characterized to be 2,3-dimetyl-5,6-bispyrazyl-2-hexene.

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A Clock Regenerator using Two 2nd Order Sigma-Delta Modulators for Wide Range of Dividing Ratio

  • Oh, Seung-Wuk;Kim, Sang-Ho;Im, Sang-Soon;Ahn, Yong-Sung;Kang, Jin-Ku
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.1
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    • pp.10-17
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    • 2012
  • This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

ON CERTAIN SUBCLASS OF STARLIKE FUNCTIONS OF ORDER ${\alpha}\cdot$ AND TYPE $\beta$

  • Aouf, M.K.
    • East Asian mathematical journal
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    • v.5 no.1
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    • pp.35-47
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    • 1989
  • Let $S_o*({\alpha},{\beta},{\mu})$ denote the class of functions $f(z)=a_1z-{\sum}{\limit}^{\infty}_{n=2}\;a_nz^n$ analytic in the unit disc $U=\{z:{\mid}z{\mid}<1\}$ and satisfying the condition $${\mid}\frac{\frac{zf'(z)}{f(z)}-1}{(1+\mu)\;\beta(\frac{zf'(z)}{f(z)}-\alpha)-(\frac{zf'(z)}{f(z)}-1)}\mid<1$$ for some $\alpha(0{\leq}{\alpha}<1),\;{\beta}(0<{\beta}{\leq}1),\;{\mu}(0{\leq}{\mu}{\leq}1)$ and for all $z{\in}U$. And it is the purpose of this paper to show a necessary and sufficient condition for the class $S_o*({\alpha},{\beta},{\mu})$, some results for the Hadamard products of two functions f(z) and g(z) in the class $S_o*({\alpha},{\beta},{\mu})$, the distortion theorem and the distortion theorems for the fractional calculus.

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A Fast-Locking All-Digital Frequency Multiplier (고속-락킹 디지털 주파수 증배기)

  • Lee, Chang-Jun;Kim, Jong-Sun
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1158-1162
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    • 2018
  • A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

A Frequency Tunable and Compact Metamaterial Peano Antenna (주파수 가변 및 소형 Metamaterial Peano Antenna)

  • Lee, Dong-Hyun;Jang, Kyung-Duk;Park, Wee-Sang
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.866-872
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    • 2007
  • In this paper, we present a frequency tunable and compact antenna which consists of a first-order Peano curve, two shorting posts, and two inductors which are serially connected between the posts and the edge of the Peano curve. By properly choosing the inductance of two inductors, the operating frequency of the antenna can be controlled without sacrificing the fractional bandwidth. To give good demonstration of the operating mechanism, the equivalent circuit of this antenna is included. To validate the simulation results, we have fabricated the several antennas of being integrated with different inductors, and the measured results show a good agreement with the simulated ones. The measured results reveal that the operating frequency is shifted from 1.47 GHz to 0.586 GHz without the decrease of the input impedance bandwidth. In case of integrating two inductors of 91nH and 470nH, the electric size of the antenna is only $0.0246 {\lambda}{\times}0.0246{\lambda}{\times}0.0114{\lambda}$. The measured fractional bandwidth$(S_{11}{\leq}-10 dB)$ and the radiation efficiency of the antenna are 5.22% and 47.25%, respectively.