• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.191-192
• /
• 2007

This paper presents a 900MHz fractional-N frequency synthesizer for radio frequency identification (RFID) reader using $0.18{\mu}m$ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900MHz VCO is generated by a 1.8GHz VCO followed by a frequency divider. The settling time of the synthesizer is less than $20{\mu}m$. The frequency synthesizer achieves the phase noise of -105.6dBc/Hz at 200kHz offset. The frequency synthesizer occupies an area of $1.8{\times}0.99mm^2$, and dissipates 8mA from a low supply voltage of 1.8V.

• ETRI Journal
• /
• v.45 no.1
• /
• pp.119-130
• /
• 2023

We propose a quantized gradient search algorithm that can achieve global optimization by monotonically reducing the quantization step with respect to time when quantization is composed of integer or fixed-point fractional values applied to an optimization algorithm. According to the white noise hypothesis states, a quantization step is sufficiently small and the quantization is well defined, the round-off error caused by quantization can be regarded as a random variable with identically independent distribution. Thus, we rewrite the searching equation based on a gradient descent as a stochastic differential equation and obtain the monotonically decreasing rate of the quantization step, enabling the global optimization by stochastic analysis for deriving an objective function. Consequently, when the search equation is quantized by a monotonically decreasing quantization step, which suitably reduces the round-off error, we can derive the searching algorithm evolving from an optimization algorithm. Numerical simulations indicate that due to the property of quantization-based global optimization, the proposed algorithm shows better optimization performance on a search space to each iteration than the conventional algorithm with a higher success rate and fewer iterations.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.7
• /
• pp.3370-3392
• /
• 2017

Next Generation Beyond 4G/5G systems will rely on the deployment of small cells over conventional macrocells for achieving high spectral efficiency and improved coverage performance, especially for indoor and hotspot environments. In such heterogeneous networks, the expected performance gains can only be derived with the use of efficient interference coordination schemes, such as Fractional Frequency Reuse (FFR), which is very attractive for its simplicity and effectiveness. In this work, femtocells are deployed according to a spatial Poisson Point Process (PPP) over hexagonally shaped, 6-sector macro base stations (MeNBs) in an uncoordinated manner, operating in hybrid mode. A newly introduced intermediary region prevents cross-tier, cross-boundary interference and improves user equipment (UE) performance at the boundary of cell center and cell edge. With tools of stochastic geometry, an analytical framework for the signal-to-interference-plus-noise-ratio (SINR) distribution is developed to evaluate the performance of all UEs in different spatial locations, with consideration to both co-tier and cross-tier interference. Using the SINR distribution framework, average network throughput per tier is derived together with a newly proposed harmonic mean, which ensures fairness in resource allocation amongst all UEs. Finally, the FFR network parameters are optimized for maximizing average network throughput, and the harmonic mean using a fair resource assignment constraint. Numerical results verify the proposed analytical framework, and provide insights into design trade-offs between maximizing throughput and user fairness by appropriately adjusting the spatial partitioning thresholds, the spectrum allocation factor, and the femtocell density.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.800-804
• /
• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.4
• /
• pp.707-714
• /
• 2012

After a single-stage, second-order, multiple-feedback ${\Delta}-{\Sigma}$ modulator and a two-stage, second-order MASH ${\Delta}-{\Sigma}$ modulator were analyzed and simulated using Simulink and Matlab and their characteristics were compared, the following result was obtained: 1) The two ${\Delta}-{\Sigma}$ modulators do not have group delay distortion. 2) The characteristics of the noise shaping are nearly identical. As a result of the noise shaping, the power spectral densities have slope of 40 dB/dec. 3) There was no spurious tone. 4) The input range of the two modulators is from -1 to +1 in common. 5) Because the output of the two-stage MASH modulator is 2-bits (4-levels), design of frequency dividers and charge pumps of PLL are more demanding.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.65-74
• /
• 2010

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.75-82
• /
• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Journal of Biomedical Engineering Research
• /
• v.25 no.6
• /
• pp.439-445
• /
• 2004

Diffusion tensor image(DTI) exploits the random diffusional motion of water molecules. This method is useful for the characterization of the architecture of tissues. In some tissues, such as muscle or cerebral white matter, cellular arrangement shows a strongly preferred direction of water diffusion, i.e., the diffusion is anisotropic. The degree of anisotropy is often represented using diffusion anisotropy indices (relative anisotropy(RA), fractional anisotropy(FA), volume ratio(VR)). In this study, FA images were obtained using different gradient schemes(N=6, 11, 23, 35. 47). Mean values and the standard deviations of FA were then measured at several anatomic locations for each scheme. The results showed that both mean values and the standard deviations of FA were decreased as the number of gradient directions were increased. Also, the standard error of ADC measurement decreased as the number of diffusion gradient directions increased. In conclusion, different gradient schemes showed a significantly different noise performance and the schem with more gradient directions clearly improved the quality of the FA images. But considering acquisition time of image and standard deviation of FA, 23 gradient directions is clinically optimal.

• ETRI Journal
• /
• v.36 no.3
• /
• pp.352-360
• /
• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 1998.04a
• /
• pp.17-24
• /
• 1998

압축기의 종류는 크게 dynamic type과 positive displacement type으로 우선 나눌 수 있다. 전자는 제트엔진에 사용되는 압축기에서 보는 바와 같이 기체의 속도를 변화시켜 동압을 정압으로 바꾸어 압력을 얻는 경우이다. 후자는 기체를 둘러싼 체적을 줄여서 압력을 얻는데 가전제품에 쓰이는 냉각용 압축기의 대부분의 종류가 이에 해당된다. 압축 기체의 종류에 따라 공기 압축기, 가스 압축기, 냉각용 압축기로도 나눌 수 있겠다. 냉각용 압축기는 다시 여러 가지 방법으로 분류할 수 있겠지만, 구동 모타의 용량이나 냉각 용량에 따라, 대형, 소형으로 분류하거나, 압축기를 둘러싼 셀의 구조에 따라 밀폐형과 반 밀폐형으로 나눌 수 있다. 밀폐형은 냉매를 반 영구적으로 보충할 필요가 없도록 용접형 셀을 가진 구조로 압축기를 다시 열어서 보수할 수가 없다. 냉장고나 냉방기 같은 가전 제품에 쓰이는 압축기는 대부분 소형 밀폐형이 되겠다. 산업용의 중,대형 압축기는 보수의 목적으로, 자동차 냉방용 압축기는 동력이 엔진축에서 공급되는 구조 상의 이유로 반 밀폐형이 채택된다. 보수가 사실상 불가능한 밀폐형의 구조 상 소형 냉장용 압축기는 거의 무한 수명을 감안한 설계를 요하게 되고, 이것이 압축기의 보수적인 설계 및 개발 성향에 어느 정도 영향을 주었다고 볼 수 있다. 이런 소형 밀폐형 압축기(positive displacement, fractional horsepower, hermetic compressor)에 관한 연구의 소개가 이 글의 주 관심이 되겠다. 압력을 얻기 위해 체적을 변화시키는 mechanism도 여러 가지가 있는 바, 왕복동식 피스톤(reciprocating piston) 압축기가 가장 오랫동안 사용되어 온 구조이다. 회전식으로 압축을 얻는 방식으로는 로타리 피스톤식, 스크류식, 스크롤식 압축기가 있다. 로타리 피스톤(rotary piston)식 압축기는 약 20여년 전 부터 냉방용 압축기에서부터 널리 쓰이게 되었다. 약 10여년전부터 상용화 된 스크롤(scroll) 형 압축기도 현재 상대적으로 용량이 큰 가정용 냉방기를 중심으로 많이 쓰이고 있다. 스크류형 압축기는 보통 중대형 상업용에 주로 쓰인다.