Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A CMOS Fractional-N Frequency Synthesizer for DTV Tuners

DTV 튜너를 위한 CMOS Fractional-N 주파수합성기

  • Ko, Seung-O (Dept. of Electronics Engineering, University of Incheon) ;
  • Seo, Hee-Teak (Dept. of Electronics Engineering, University of Incheon) ;
  • Park, Jong-Tae (Dept. of Electronics Engineering, University of Incheon) ;
  • Yu, Chong-Gun (Dept. of Electronics Engineering, University of Incheon)
  • Received : 2010.03.04
  • Published : 2010.04.26
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Abstract

The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a $0.18{\mu}m$ CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%) and frequency steps of 26~42.5MHz(${\pm}$8.25MHz/V,${\pm}$24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than $10{\mu}$sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm${\times}$1.8mm.

최근 TV 방송의 새로운 시장인 DTV 시장이 넓어지면서 DTV 튜너에 대한 요구도 많아지고 있다. DTV 튜너를 설계하는 데에는 많은 어려운 부분이 있지만, 가장 어려운 부분 중에 하나가 주파수합성기이다. 본 논문에서는 DTV 튜너를 위한 주파수합성기 회로를 $0.18{\mu}m$ CMOS 공정을 사용하여 설계하였다. 설계한 주파수합성기는 DTV(ATSC)의 주파수 대역(54~806MHz)을 만족한다. 하나의 VCO를 사용하여 광대역을 만족시킬 수 있는 구조를 제안하고, LO pulling 효과를 최소화 하기위하여 1.6~3.6GHz 대역에서 동작하도록 설계하였다. 또한 고주파 대역과 저주파 대역에서의 VCO 이득의 차이와 주파수 간격의 변화를 줄여 안정적인 광대역 특성을 구현하였다. 모의실험 결과, 설계한 VCO의 이득은 59~94MHz(${\pm}$17.7MHz/V,${\pm}$23%)이고, 주파수 간격은 26~42.5MHz (${\pm}$8.25MHz/V,${\pm}$24%)이며, tuning range는 76.9%이다. 설계된 주파수합성기의 위상잡음은 100kHz offset에서 -106dBc/Hz이고, 고착시간은 약 $10{\mu}s$ 정도이다. 설계된 회로는 1.8V 전원전압에서 20~23mA의 전류를 소모하며 칩 면적은 PAD를 포함하여 2.0mm${\times}$1.8mm이다.

Keywords

References

  1. United States Advanced Television Systems Committee, "ATSC Digital Television Standard," September 1995.
  2. Supisa Lerstaveesin. et al., "A 48-860MHz CMOS Low-IF Direct-Conversion DTV Tuner," IEEE J.Solid-State Circuit, vol. 43, no. 9, pp.2013-2024 Sep. 2008. https://doi.org/10.1109/JSSC.2008.2001900
  3. J. Xiao, et al.,"Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting," VLSI Design, Article ID 71974, 2007.
  4. J. van Sinderen, et al., "A 48-860MHz digital cable tuner IC with integrated RF and IF selectivity," ISSCC Dig. Tech. Papers, pp.444-506, Feb. 2003.
  5. Jecheol Moon, Yong Moon "A Design of Wideband Frequency Synthesizer for Mobile-DTV Applications," Journal of IEEK, vol. 45-SD, NO. 6, pp. 40-49, June 2008.
  6. B. Miller, B. Conley, "A Multiple Fractional Divider," IEEE transactions on instrumentation and measurement, vol. 40, pp. 578-583, June 1991. https://doi.org/10.1109/19.87022
  7. M. H. Perrott, T. L. Tewksbury III, and C. G. Sodini, A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GMSK Modulation, IEEE J. Solid-State Circuits, vol. 32, pp. 2048-2060, Dec.1997. https://doi.org/10.1109/4.643663
  8. N. M. Filiod, T. A. D. Riley, Calvin Plett, M. A. Copeland, An Agile ISM Band Frequency Synthesizer with Built-In GMSK Data Modulation, IEEE J. Solid-State Circuits, vol. 33, No. 7, pp. 998-1008, July. 1998. https://doi.org/10.1109/4.701242
  9. B. H. Park and P. E. Allen, A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrated LC VCO For Wireless Communications, Proc. IEEE Custom Integrated Circuits Conf., pp. 26.4.1-26.4.4, 1998.
  10. W. Rhee, B. S. Song, A. Ali, A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order $\Sigma\Delta$ Modulator, IEEE J. Solid-State Circuits, vol. 35, No. 10, pp.1453-1460, Oct. 2000. https://doi.org/10.1109/4.871322
  11. Seon-Ho Han, Yong-Sik Youn, Cheon-Soo Kim, Hyun-Ku Yu, Mun-Yang Park, "Prescaler using complementary clocking dynamic flip-flop", Electronics Letters, vol. 39, pp. 709-710, May. 2003. https://doi.org/10.1049/el:20030478
  12. Moriaki Mizuno, "A 3mW 1.0-GHz silicon-ECL dual-modulus prescaler IC," IEEE J. solid-state circuit, vol. 27, pp.1794-1798, Dec. 1992. https://doi.org/10.1109/4.173107
  13. Heydari, P., Mohanavelu, R., "Design of ultrahigh-speed low-voltage CMOS CML buffers and latches", Very Large Scale Integration (VLSI) Systems, Transactions on IEEE, vol.12. pp.1081-1093, 2004. https://doi.org/10.1109/TVLSI.2004.833663
  14. Yu-che Yang. et al., "A Single-VCO Fractional-N Frequency Synthesizer for Digital TV Tuners," IEEE J. Solid-State Circuit, pp.1545-1548 June. 2007.
  15. Jeawook Shin. et al., "A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18um CMOS," IEEK JSTS, vol. 7, no.4, pp.267-273, Dec. 2007.