• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.12
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• pp.1671-1677
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• 2018

In this research, the collision detection system based on insect's visual interneuron has been designed. The lobula giant movement detector (LGMD) corresponds to the movement value that increases in direct collision process. If the collision is detected by the LGMD only, it could generate a crash warning even in a non-collision situation, resulting in a lot of false alarms. Directionally sensitive movement detectors (DSMD) are directionally sensitive algorithm based on the elementary movement detectors (EMD) in four directions (up, down, left, and right). In this paper, we propose an efficient VLSI architecture for a realtime collision detection system that is robust to the surrounding environment while improving accuracy. The proposed architecture is synthesized with Dongbu Hightech 110nm standard cell library and shows 333MHz of maximum operating frequency and requires 8400 gates with about 16.5KB of internal memories.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1025-1031
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• 2007

This paper proposes an area-efficient pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving antennas. Since the MIMO-OFDM system transmits multiple data streams, the complexity for the MIMO-OFDM system with a single-channel FFT processor increases linearly with the increase of the number of transmit channels. The proposed FFT processor is based on multi-channel structure, and therefore it can efficiently support multiple data streams. With the mixed radix algorithm, the number of non-trivial multiplications of the proposed FFT processor is decreased. The proposed FFT processor is synthesized with CMOS $0.18{\mu}m$ process and reduces the logic gates by 25% over a 4-channel Radix-4 multi-path delay commutator (R4MDC) FFT processor. Since the MIMO-OFDM FFT processor is one of the largest modules in the systems, the proposed FFT processor will be a vast contribution improvement to the low complexity design of MIMO-OFDM systems.

• Journal of Construction Engineering and Project Management
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• v.10 no.1
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• pp.16-32
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• 2020

Cost and time control of projects is important in preventing project failure. However, achieving effective cost and time control in practice is often challenging. The challenges of project cost and time control in practice are investigated by carrying out a questionnaire survey on the top 150 construction contractors in the UK followed by in-depth semi-structured interviews of practitioners from 15 construction companies in the country. Quantitative analysis reveals that design change is the most important factor inhibiting the ability of UK contractors from effectively controlling both the cost and time of construction projects. Four of the top five factors inhibiting effective cost control are also the top factors inhibiting effective time control albeit in a different order. These top factors-design changes, inaccurate evaluation of project time/duration, risk and uncertainty, non-performance of subcontractors and nominated suppliers were also found to be endogenous factors to the project. Additionally, qualitative analysis of the interviews reveals 16 key challenges to prevent for effective project cost and time control in practice. These are classified into four categorised based on where they stem from as follows; from the organisation (1. Lack of integration of cost and time during project control, 2. lack of management buy-in, 3. complicated project control systems and processes, 4. lack of a project control training regime); from the construction management/project management approach (5. Lapses in integration of interfaces, 6. project control not being implemented from the early stages of a project, 7. inefficient utilisation and control of labour, 8. limited time devoted to planning how a project will be controlled at the outset); from the client; (9. Excessive authorisation gates, 10. use of adversarial and non-collaborative forms of contracts, 11. communication problems within client set-up, 12. obstructive client representatives) and; from the project team (13. Lack of detailed/complete design, 14. lack of trust among the project partners, 15. limited time devoted to project control on site, 16. non-factual reporting). The study posits that knowledge of these project control inhibiting factors and challenges is the first step at ensuring they are avoided and enable the implementation of a more effective project cost and time control process in practice.

• Journal of the Korean Institute of Landscape Architecture International Edition
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• no.1
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• pp.89-101
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• 2001

The purpose of this study ins to verify the characteristic location of Byungyoung Castle, physical type, inside spatial organization, and the scheme of Byungyoung Castle. The study utilizes historic literature, ancient maps related to Byungyoung Castle, topographical and cadastral maps which were published under the rule of Japanese Imperialism Castle, topographical and cadastral maps which were published under the rule of Japanese Imperialism and the topographical maps which were made recently by National Geographic Institute with various scales. The methodology of the study is to interpret the contents from the historic literature on the site map. The methodology of the study is to interpret the contents from the historic literature on the site map. The result of the study is as follows; Byungyoung Castle does duty as a defensive base for the entire country and has a specific character of location that has the dual function of a mountain fortress for national defense and of a village fortress for the town. Byungyoung Castle has four gates on four sides and has a oval shape very close to a circular form. The road construction inside the castle is composed basically of a cross shape. Byungyoung is located in the northwest area of this major road system. The private houses that lie along the north-south road are build up at the core area of the lower level and the town market built up around the south gate becomes the heart of life for the people. Schematically, it has the same pattern as regular village fortress, in that the houses for the guests and the houses for the public office are arranged to the east and the west. It is considered that there is certain functional parallel between Byungyoug Castle and Ulsan castle because there are no facilities for sacrificial rites no institutional budding.

• KCID journal
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• v.18 no.1
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• pp.44-57
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• 2011

The status of fishway installed in domestic dikes showed a cascade types and sluice gate types 36% (four sites) and 64% (seven sites), respectively. Fishway of cascade type was constructed four sites (Iweon, Busa, Geum river, Haenam) and only Geum river was one of them has operated much more effectively since remodeling in a fishway and fishways of the others was not operated because of several problems like a desalination, a shortage of inflow water and variation of management elevation. Fishway of sluice gate type was installed seven sites and three sites (Yeongsan, Yeongam, Geumho) one of them were continuously operated until now. This results has a interesting interpretations. Prolonged discharge of inductive water from fishway can positively affect not only ascending of fishes but also fish fauna of around of the sea. The others of a sluice gate fishway were not operated because of seawater circulation through sluice gate until now. The closed reasons of fishway in domestic dikes may be summarized as follows: impassibility of sluice gate open by shortage of inflow water, problem of proper operating by long distance of between fishway and management office, absence of operating manual, seawater circulation, lack of fishway operating awareness. It was takes a long time for solution of hardware part but software part can be to find the answer through making a fishway operation manual and development of education program for manager. In this paper we deal with fishway in domestic dikes. Proper fishway control by manager was essential for ascending of migration fishes especially at fishway installed in dikes. Thus it was necessary to make manual for fishway operation and effort of continuously maintenance.

• The Journal of Society for e-Business Studies
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• v.20 no.1
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• pp.183-199
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• 2015

Due to the Four Major Rivers Restoration Project, Nakdong River Estuary Barrage's designed flood quantity has been largely increased, and this has caused to construct several drainage gates at the right side of Eulsukdo island to secure the safety of downstream river area. For successful functioning of Nakdong River Estuary Barrage, such as flood control, disaster prevention, and the securing of sufficient water capacity, drainage gates at the both sides of island have to operate systematically and reliably. To manage this under restricted personnel and resources, we have implemented the IOS (Integrated Operation System) by integrating previous facilities and resources via information and communication technologies. The IOS has been designed to have higher availability and fault tolerance to function continuously even with the partial system's failure under the emergency situation like flood. Operators can use the system easily and acknowledge alarms of facilities through its IWS (Integrated Warning System) earlier. Preparing for Integrated Water Resources Management and Smart Water Grid, the architecture of IOS conformed to open system standards which will be helpful to link with the other systems easily.